Part Number: LMK00301 Tool/software: In an LVDS output configuration, is there any issue using CLKoutX_TYPE1 as a dynamically controlled output disable pin?
Part Number: LMK00301
Tool/software:
Hi, The datasheet feature says the LVDS frequency range is DC to 2100MHz, but the specification table says 1.0GHz to 1.6GHz, and Figure 7-2 shows the LVDS Output Swing (VOD) vs. Frequency range as 100MHz to 1.3GHz.…
Part Number: LMK00301 Other Parts Discussed in Thread: LMK1D2102 Tool/software: Dear Experts,
We are selecting a clock buffer that meets the requirements of one 27MHz differential clock input (LVDS) and two 27MHz differential clock outputs (LVDS). We…
Part Number: LMK00301 Tool/software: What is the expected switching time (new output after changing CLKin_SEL) for the LMK00301?
Normally I am observing a very fast switching time, but occasionally I see about 12 usec, which seems long.
Thanks
Part Number: LMK00301 Tool/software: Could you, please, provide what the Junction-to-board thermal resistance information for the part ( LMK00301ARHST )?
Hello Jeff,
We ran the traces with terminating unused outputs and without terminating unused outputs. As you can see from the graph, the results are very similar, so not terminating an unused output should not impact the output of the LM00301. The raw…
Part Number: LMK00301 Under the conditions of LVPECL, Vcco=3.3V, CLKin=156.25MHz, JitterADD (Additive RMS Jitter, Integration Bandwidth 10 kHz to 20 MHz) of LMK00301 is typ:54fs, max78:fs. Under the conditions of LVDS, Vcco=3.3V, CLKin=156.25MHz, JitterADD…
Part Number: LMK00301 Hi,
Does Bank A and Bank B have any phase delay if we configure both bank a and bank b with same output signal type (such as LVDS)?
What is the phase delay spec between Bank A and Bank B?
Thanks!
Part Number: LMK00301 The LMK00301 Datasheet Sec 7.5 (Electrical Characteristics) states that the Differential Input Common Mode Voltage (Vcmd) is 0.25V MIN.
If AC coupling is used, like you say it can be, is an external bias network required to create…
