Part Number: LMK00301 Hi,
Does Bank A and Bank B have any phase delay if we configure both bank a and bank b with same output signal type (such as LVDS)?
What is the phase delay spec between Bank A and Bank B?
Thanks!
Part Number: LMK00301 The LMK00301 Datasheet Sec 7.5 (Electrical Characteristics) states that the Differential Input Common Mode Voltage (Vcmd) is 0.25V MIN.
If AC coupling is used, like you say it can be, is an external bias network required to create…
Part Number: LMK00301
Hi there,
We have a CPU output PCIe GEN 3.0 ref clock 100MHZ, it needs to be buffered two outputs.
we used dedicated clock buffer like ICS9DB102 before, for GEN2.0
Now we hope to know how to determine if LMK00301 can support PCIE…
Part Number: LMK00301 Hi,
I am using 3.3V LVDS output of 125MHz from LMK00301A. This output is given as an input to Ethernet QSGMII PHY 88E1548's REFCLKP/N inputs.
I have used 0.01uF caps as AC coupling caps and there is a 100 ohm differential termination…
Part Number: LMK00301 Hi Team,
As far as i can see in order to configure the different outputs banks of the buffer you have to send either '1' or '0' the the designated pins.
Since this device is the clock source for my FPGA when startup…
Part Number: LMK00301 Hello Experts,
We need your assistance with the customer's query below.
I am using the LMK00301 to buffer a calibration signal. The signal is periodical on a frequency between 1MHz and 10MHz but is not a 50% duty cycle. I…
Part Number: LMK00301 Other Parts Discussed in Thread: LMK00338 , It looks like both the LMK00301 and LMK00338 meet the additive jitter requirements for PCIe Gen 5 clock distribution, but it isn't specified in the data sheet. Can you confirm the LMK00301…
Part Number: LMK00301 The data sheet for the LMK00301 page 26 regarding AC coupling appears to be completely wrong and in need of a re-write. Contrary to what the whole page is about, the LVDS driver output DOES NOT NEED A DC CURRENT RETURN PATH. No LVDS…
Part Number: LMK00301 Hi Team,
Our customer is using the LMK00301SQE/NOPB and need to pass a synchronisation pulse in the buffer. He would like to know the minimum pulse width he needs and the amount of jitter he can expect (the slew rate is around 2V/ns…
