Answered

• LMK01000: use of LMK01000 for JESD204 fanout buffer and SYSREF divider

  

  shay maoz

  Resolved

  Part Number: LMK01000 Tool/software: Hi I consider using the LMK01000 for JESD204 fanout buffer and SYSREF divider. input clock 120MHz output clocks 120MHz: ------------------------------ 2 x LVPECL 2x LVDS output clocks SYSREF - 8MHz…

  • Resolved

  • over 1 year ago
  • Clock & timing
  • Clock & timing forum

• LMK01000: How to Terminate Unused LVPECL Clock Outputs

  

  D Gauthier

  TI Thinks Resolved

  Part Number: LMK01000 Tool/software: It's unclear from the LMK01000 datasheet how to treat unused LVPECL outputs (i.e., CLKOUT[7..3]) - should they be left floating or terminated through emitter resistors? Thanks, Devin

  • 6 months ago
  • Clock & timing
  • Clock & timing forum

• LMK01000: 1:2 Fanout Buffer Availability

  

  Sakthi R

  TI Thinks Resolved

  Part Number: LMK01000 Other Parts Discussed in Thread: LMK1D1204 , LMK1D2102 Hello TI Team, I am searching for the 1:2 Fanout Buffer (max output Freq of 200 MHz) which accepts the Single Ended 50 Sine Wave Ohm Input OCXO and Splits into two Differential…

  • over 1 year ago
  • Clock & timing
  • Clock & timing forum
Answered

• LMK01000: Too many VCC. What are the diferences?

  

  TI-CSC

  Resolved

  Part Number: LMK01000 Hello E2E Experts, Good day. 1. May I ask what are the differences between different VCC names? VCC1, VCC2..., etc. 2. Is it internally connected? 3. What is the reason behind many bypass capacitors for each Vcc pin? Regards…

  • Resolved

  • over 2 years ago
  • Clock & timing
  • Clock & timing forum

• LMK01000: Failure of 1 LVDS pair during testing

  

  Vikas Kumar40

  Part Number: LMK01000 Good Morning I am using Clock buffer LMK01000 for LVDS clock generation. Currently I am using single channel for testing. After programming, the clock buffer is able to generate the required clock but issue has come up during integration…

  • over 3 years ago
  • Clock & timing
  • Clock & timing forum

• LMK01000: About Fclkin and divide

  

  user5959213

  TI Thinks Resolved

  Part Number: LMK01000 Hi all, From the datasheet,the relationship of them is as follow: But when i test the LMK01000 DEMO,the Fclkin=1474.56M and the divider is set to 4,it also works. So which one is correct?

  • over 5 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• LMK01000: Delay Noise Floor Information

  

  archer01

  Resolved

  Part Number: LMK01000 In the "CLKout DELAYS" section of the LMK01000 datasheet it states "When the delay is enabled it adds to the output noise floor". The same section states "Refer to the Typical Performance Characteristics plots for the Delay Noise…

  • Resolved

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum
Answered

• LMK01000: Non-clocking application: SE-to-LVDS translator

  

  Ryan.Bishop

  Resolved

  Part Number: LMK01000 Other Parts Discussed in Thread: LMK01801 Hello, I am looking for a part to do SE-to-LVDS translation with ultra-low skew. Our dedicated LVDS drivers couldn't reach the accuracy we need, so we are considering clock buffers for…

  • Resolved

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum

• LMK01000: Additive Jitter at 50 MHz

  

  Mark Guastaferro

  TI Thinks Resolved

  Part Number: LMK01000 Is there any data showing the additive jitter with a 50 MHz input and a 50 MHz LVPECL output (divider and delay bypassed)? Lowest frequency shown in data sheet is 200 MHz output and footnote suggests there may be characterization…

  • over 6 years ago
  • Clock & timing
  • Clock & timing forum

• LMK01000: Rise/Fall time of LVPECL output

  

  Toshi

  TI Thinks Resolved

  Part Number: LMK01000 Simon, thank you very much for your help. Well, this is just actual measurement data, and you don't have MIN and MAX spec at this time, correct ?

  • over 7 years ago
  • Clock & timing
  • Clock & timing forum

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