Hello Shay,
Sorry for the late reply. Yes, the 150ps also applies to 120MHz input.
shay maoz said: any relation between the clock input period to the delay adjustment?
Yes, they are related to the input clock + a 400ps delay. The extra delay comes from…
Hello Sakthi,
That decision is up tp you. The 2102 has two inputs and two outputs, so you would use one input that feeds into both outputs. The 1204 has one input and 4 outputs, so you could just leave the unused outputs floating.
Best,
Andrea
Part Number: LMK01000 Hello E2E Experts,
Good day.
1. May I ask what are the differences between different VCC names? VCC1, VCC2..., etc.
2. Is it internally connected?
3. What is the reason behind many bypass capacitors for each Vcc pin?
Regards,
CS…
Part Number: LMK01000 Good Morning I am using Clock buffer LMK01000 for LVDS clock generation. Currently I am using single channel for testing. After programming, the clock buffer is able to generate the required clock but issue has come up during integration…
The discrepancy may be because I am also including the current for the LVPECL emitter bias resistors of 240 ohms. Either way, 1 to 1.1W is too much power for what I am trying to do. I am now looking at LMK01000 to generate Three 200MHz clocks and Two 1MHz…
Part Number: LMK01000 Hi all,
From the datasheet,the relationship of them is as follow:
But when i test the LMK01000 DEMO,the Fclkin=1474.56M and the divider is set to 4,it also works.
So which one is correct?
Part Number: LMK1C1104 Other Parts Discussed in Thread: LMK01000 , LMK04832 , SN65LVELT23 , LMX2820 , LMX2594 , DDS39RF10 Tool/software: Hi,
I would like to generate single ended CMOS clocks (< 250 MHz) with 10%, 25%, 50% and 75% duty cycle on the board. …
Part Number: LMK01000 Other Parts Discussed in Thread: LMK01801 Hello,
I am looking for a part to do SE-to-LVDS translation with ultra-low skew. Our dedicated LVDS drivers couldn't reach the accuracy we need, so we are considering clock buffers for this…
Part Number: LMK01000 In the "CLKout DELAYS" section of the LMK01000 datasheet it states "When the delay is enabled it adds to the output noise floor". The same section states "Refer to the Typical Performance Characteristics plots…
Part Number: LMK01000 Is there any data showing the additive jitter with a 50 MHz input and a 50 MHz LVPECL output (divider and delay bypassed)?
Lowest frequency shown in data sheet is 200 MHz output and footnote suggests there may be characterization…
