Hi Dean,
Thanks for the details you provided. I believe the customer's main concern was that there was an clock signsal comming out of the LMK03002 when the input reference clock is removed. They were concerned because in their applicaiton it is possible…
Other Parts Discussed in Thread: LMK03002 Hi Team!
I had a few questions regarding the LMK03002.
On the datasheet, it states that bit 31 is the RESET bit in register R0. Is this the only thing that is present in register 0?
Also, on page 15, section…
Hello Nikhil,
Do you have any restrictions on your input frequency? What is the range of clock frequencies you are wanting to provide? Are there any other clocks needed in the system, what are those clock frequencies?
* You might try using the clock…
Other Parts Discussed in Thread: LMK03002 , CODELOADER Hi,
I have a question regarding the LMK03002. We are using it on a new design to produce a 200MHz clock from a 10MHz input reference. I believe I have the registers set up correctly to do this:…
Other Parts Discussed in Thread: LMK00301 , LMK04100 , LMK04906 , LMK03002 , LMK04806 , CDCE62005 , CDCM6208 I'm looking for a clocking solution:
Requirements:
Two 10 MHz reference inputs (LVTTL single ended) with input select signal.
Output 100…
You may consider using LMK04906 (6-output dual loop jitter cleaner/clock gen) configured for Single Loop mode (PLL2+integrated VCO). You can use Clock Design Tool to enter a model of your input clock phase noise and simulate the output clock phase noise…
Is this case on an evaluation board or your own design?
- If your own board, can you share schematic? LMK03002 outputs are all LVPECL which require a DC path to ground. If AC coupling have emitter resistor been placed?
- What is the slew rate of the…
Other Parts Discussed in Thread: CLOCKDESIGNTOOL , LMK03033 , LMK03002 , LMK03806 , ADS6442 , LMK00105 , CDCE925 , CDCLVC1310 Hello!
I am looking for optimal solution (IC) to generate 32MHz clock from 10MHz reference.
The needed 32MHz frequency if…
Hello Ron,
Sorry for your trouble.
Two issues are going on here.
1) The LMK0482x profiles for the CDT does not support the SYSREF divider. So the max divide is 32 which doesn't allow it to find 19.2 MHz.
- A workaround is to put a multiple of…
