Hi Arvind,
The VCXO output and all the outputs on the first LMK04828 are 100MHz. The outputs from the second LMK04828 and LMK03806 are variable for this SDR application.
RMS jitter requirement for devices supplied through the second LMK04828 and…
Hi Toshi-San,
Can the customer try the following:
1) Reduce the value of the AC coupling capacitor: Not sure what value it is at now but they can try reducing it
2) Change CLKoutX_TYPE = 5 (2VPECL mode) if they can tolerate a higher differential…
Other Parts Discussed in Thread: DAC34H84 , LMK03806 With DAC34H84, when running in coarse mixer mode with SYNC in a single source mode and DAC PLL is disabled, we are observing the mirror signal on the spectrum.
For example, when CMIX = Fs/8 and the…
Hi Shyam,
A buffer can works as a redriver to terminate reflection caused by connector, but it can't reduce jitter. A buffer would add some additive jitter. Fortunately, CDCLVP1102 is a very low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz offset…
Other Parts Discussed in Thread: CDCM6208 , LMK03806 , CDCE62005 Hello all,
We are designing a new board based on C6678 and will include a Kintex FPGA (runs at 50 or 200 MHz), 2 ADC (50 MHz) and a PCIe Gen 2 interface between the C6678 and FPGA...My…
Depends on reference performance and ADC/DAC clock jitter requirements.
If reference is noisy (from FPGA or recovered from PHY/SerDes), we need dual PLL jitter cleaner LMK04133 (5 pairs of outputs)/ LMK04803 (12 pairs of outputs)/LMK04828 (14 pairs of…
Hi Amnon,
Which LMK part do you use? Is that LMK03806?
For 2400MHz harmonics, it's reasonable because internal VCO is running in 2400MHz, and LVPECL output drives as a squre wave, not sine wave.
For Nx50MHz spurs, it would be related your setting…
Hi Sina,
At 250MHz, I don't think you can source a standard XO. That means, you need a clock generator anyway.
If only one clock is needed, you can use LMK61E2. This device is pin compatible with a standard XO.
If multiple clocks are needed, you…
