Other Parts Discussed in Thread: LMK04133 , LMK04906 Hi, I am planning to use LMK04133 in one of my video project. For one of the video format clock generation, PLL2 phase detector frequency is comming to 43KHz. Can somebody please tell me the peak-to…
Part Number: LMK04133 Other Parts Discussed in Thread: LMK04821 The LMK04133 seems to be a good choice to sync to an incoming Audio -Wordclock of 32-192kHz being a Wordclock-Slave.. (fin_min = 1kHz in manual mode).
Our question would be:
What center…
Hi
The pdf is great, thank you so much.
just a remark; the lmk04131 was recomented to by in another post, based on my application. I am just not sure how to set it up.
My problem is that I am running a DAC and an ADC from an FPGA through a low pin…
Other Parts Discussed in Thread: SN74S124 , CLOCK-TREE-ARCHITECT , LMK61E2 , LMX2571 , LMX2572 , LMK04133 Hi
While searching for a VCO with output frequency as 27MHz , I found the part number SN74S124 . But the datasheet doesn't have any formula to…
Part Number: LMK04832-SP Other Parts Discussed in Thread: LMK04832 , LMK04821 , LMK04133 , LMK04033 , , LMX2615-SP For my design, I am trying to have the LMK04832 produce clock signals of speeds 1 GHz and 2 GHz. Now, the internal VCO0 produces frequencies…
Hi Madhu
Thank you for reply.
Additionally , let me ask you a question about LMK04133.
In the case of using a fixed VCXO , could it output multiple frequency wave ?
Once I use clock design tool , the result was following .
LMK04133 with 100MHz…
Hi Shyam,
A buffer can works as a redriver to terminate reflection caused by connector, but it can't reduce jitter. A buffer would add some additive jitter. Fortunately, CDCLVP1102 is a very low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz offset…
Depends on reference performance and ADC/DAC clock jitter requirements.
If reference is noisy (from FPGA or recovered from PHY/SerDes), we need dual PLL jitter cleaner LMK04133 (5 pairs of outputs)/ LMK04803 (12 pairs of outputs)/LMK04828 (14 pairs of…
Hello Kadeem,
Is there simulator tool to see output clock characteristics of CDCE813, like TICS pro?
This time our working condition is that input clock 24.576MHz with 4ns jitter from digital PLL output then we expect jitter reducing function of CDCE813…
