Part Number: LMK04610 Hi:
I'm trying to understand the requirements to get a deterministic skew from input-to-output on an LMK04610 using PLL2-only mode. The overall clocking architecture we have is pretty simple, in that the output clocks needed are…
Part Number: LMK04610 Other Parts Discussed in Thread: LMK1D2104 Hi TI team,
I have a generic question on the JESD204 interface for the Multi-chip synchronization.
Let's say, I'm using LMK04610 timing device in our application.
The DEVCLK and…
Part Number: LMK04610 Hi,
I am using lmk04610 on my own pcb. i am trying to configure it with my FPGA Arm core through software with SPI.
I can see that write and read are working great.
what i am trying to do is to lock PLL2. as much as i can see by…
Part Number: LMK04610 Other Parts Discussed in Thread: LMK04828 , LMK04832 Dear sirs,
I am working in a new design and I need to simulate the phase noise of outputs of LMK04610 and I have not found any simulation tool in TI to perform this simulation. …
Part Number: LMK04610 Other Parts Discussed in Thread: LMK04616 We are attempting to use the LMK04610 to synchronize to a reference source with a low phase noise VCXO and then distribute it.
We want to support 2 reference input frequencies of 10MHz and…
Part Number: LMK04610 Hi Team,
Our customer wants to check below questions for LMK04610 clock input and output, please help to check:
1. Does all clocks output are synchronized in phase?
2. If answer is Yes for question 1, does it also synchronized to…
Part Number: LMK04610 Hi,
I want to configure lmk04610 with the assistant of TICSpro (v1.7.5.0), but i notice that some register addresses on the datasheet do not math the address on the software. For example, the register PLL1EN in TICSPRO is 0x0110…
Part Number: LMK04610 I am trying to use the LMK04610 to generate a SYSREF pulse on one of the output clock pins. I am currently using the part in bypass mode (no PLLs activated, just outputs a copy of the input clock). From what I understand, in order…
Part Number: LMK04610 Hello,
I am having trouble getting the zero delay mode to work on the design I am trying to generate. In feedback mode (setting on PLL2 tab of TICS pro software) the PLL2 locks, and the output clocks are what I expect them to be…
Part Number: LMK04610
HI Derek,
I posted a question regarding single shot sysref generation . I am just writing this to say the device is working and the reason from my problem is sysref was being sent to a my fpga via decoupling caps. This caused the…