Part Number: LMK04610 Hi,
I want to configure lmk04610 with the assistant of TICSpro (v1.7.5.0), but i notice that some register addresses on the datasheet do not math the address on the software. For example, the register PLL1EN in TICSPRO is 0x0110…
Part Number: LMK04610
HI Derek,
I posted a question regarding single shot sysref generation . I am just writing this to say the device is working and the reason from my problem is sysref was being sent to a my fpga via decoupling caps. This caused the…
Part Number: LMK04610 I am trying to use the LMK04610 to generate a SYSREF pulse on one of the output clock pins. I am currently using the part in bypass mode (no PLLs activated, just outputs a copy of the input clock). From what I understand, in order…
Part Number: LMK04610 Hello,
I am having trouble getting the zero delay mode to work on the design I am trying to generate. In feedback mode (setting on PLL2 tab of TICS pro software) the PLL2 locks, and the output clocks are what I expect them to be…
Hi Ryan,
If you want to have your first LMK04610 in bypass/buffer mode, you can't be having jitter cleaner functionality.
For buffer mode, you can follow the Bypass 1 Mode, which can provide the CLKinX input to CLKout output.
For having jitter cleaner…
Hello Vinod,
Vinod Vinod said: Does this mean that the output frequencies that are derived out of PLL2 synthesizer will be at the required ppm tolerance (stringent requirement of <10ppb) faster when the PLL1 ppm is kept wider?
No. The time that it…
Part Number: LMK04610 Dear Sir,
I used CLKinX = 10MHz, VCXO = 122.88MHz. How to correct the Loss of Signal Detection setting as below? Currently, LOS always is lost of the signal. The PLL1 is locked on disable LOS function.
Part Number: LMK04610 Currently we are using the LMK04610 in our design, we are using the SIT3808AI-CF-33EM-50.000000X as VCXO and the DSC1101DL5-050.0000 as CLKIN1.
At the CTRL_VCXO there is a 100nF capacitor.
What we see is that the PLL1 lock-detect…
Part Number: LMK04610 Please can provide assistance in the configuration for the LMK04610.
The Input clock is (CLK0) 10MHz. The External VCXO is 122.88MHz. The output clock is 122.88MHz.
Currently, PLL1 didn't lock of 10MHz of the input clock. If the…
Part Number: LMK04610 Currently we are using the LMK04610 in our design, we are using the SIT3808AI-CF-33EM-50.000000X as VCXO and the DSC1101DL5-050.0000 as CLKIN1. At the CTRL_VCXO there is a 100nF capacitor. What we see is that the PLL1 lock-detect is…
