Part Number: LMK04816 Tool/software: Hi,
We have a board using the LMK04816, and due to an error the chip was supplied with 5V instead of 3.3V. We have rectified the issue and will replace the chip itself but need to know if the digital outputs (pins…
Part Number: LMK04816 Hi,
Engineer is working on LMK04816BISQE/NOPB SI simulation and not able to find the selection that set pin 39 and 40 OSCOUT10 to LVDS or LVCMOS.
IBIS model selector only shows LVPECL. Could you help to rectify this issue ?
Rgds…
Hi Joe,
LMK04906 also share the same architecture as LMK04816 and it should also supposed to support the undisclosed mode Mode Mux 13. but I would verify once again from design side.
Thanks!
Regards,
Ajeet Pal
Hi Joe,
Great to hear.
Joe Suat Chai said: This “One-time Cal” could be done in any temp, since there is little dependency on temp. This is important because we already have units in the field, and forcing a customer to do this at 25C could be problematic…
Part Number: LMK04816 As I know, the primary goal of 0-delay is to maintain a fix delay between CLKin and CLKout in dual-loop mode or maintain a fix delay between OSCin and CLKout in single-loop mode. That is, the delay is not zero but is a deterministic…
Part Number: LMK04816 If I would to like to use external VCO for PLL2, do I still have to comply to 2370 to 2600MHz range in Clock Design Tool?
Or I can choose any VCO with frequency range from 1kHz to 3100MHz as stated in fFIN in datasheet?
Part Number: LMK04816 Dear team,
My customer will use LMK04816 and they have two VCXO, one has larger VC pin input impedance(10Mohm), while other VCXO is 1Mohm. Could you help give any advice on whether VCXO Vc input impendence will have influence on PLL…
Part Number: LMK04816 Other Parts Discussed in Thread: ADC08DJ3200 , LMK04832 Hi team,
My customer considers to use LMK04816 and he is asking some questions.
Do you have estimated max value for max |TSKEW| between different Clock Group in case of LVPECL…
Part Number: LMK04816 Other Parts Discussed in Thread: PLLATINUMSIM-SW From LMK04816 datasheet:
1. PLL1 typically uses a narrow loop bandwidth (10 to 200 Hz) to:
- retain frequency accuracy of external reference clock
- suppress high offset frequency…
Part Number: LMK04816 Other Parts Discussed in Thread: LMK04805 , LMK04808 I am trying to derive a 150 MHz and 125 MHz signal from a LMK04816 that is input with a 50 MHz reference clock. When I run TICs Pro, it indicates that the PLL2 output is bounded…
