Part Number: LMK04832-SP Now we are developing a navigation payload.
When we receive a 10.23MHz clock with a jitter of +/- 2nsec, we'd like to clean the clock using a dual PLL scheme.
We use an output clock of 122.76MHz (12 times 10.23MHz).
Could…
Part Number: LMK04832-SP Hello,
I found that there is no performance degradation when an unpowered LMK input is receiving a signal for up to 10 hours of the lifetime of the device. Though, it also mentions for "short periods of time", does this mean these…
Part Number: LMK04832-SP Is there a pad on the part that needs to be tied to ground to ground the lid? If so where is this pad located?
Also regarding the heat sink. Is the only way to ground this sink by soldering it to the board?
Part Number: LMK04832-SP Other Parts Discussed in Thread: LMK04828 , Hello, When connecting LMK04832-SP LVDS differential output to FPGA differential LVDS inputs having 100ohms termination internally with AC coupling, the 560oms to close the output pins…
Part Number: LMK04832-SP Hello,
What is the max input voltage to the LMK04832-SP when it is not powered? Is there also a frequency dependency when powered off?
There is a note in the datasheet that specifies the unpowered state of the device:
"(2) When…
Part Number: LMK04832-SP Hello, how are you?
I want to ask you a question. We are working on a design of LMK04832-SP in dual loop mode.We made some tests about that mode and we noticed the PLL2 single loop mode has a better performance than dual loop…
Part Number: LMK04832-SP Hi experts
I'm using the TICS Pro Current Calculator. Can I assume that this tool provides the expected Typical current and consumption values?
How should we estimate the expected Max that could occur corresponding to this…
Part Number: LMK04832-SP Other Parts Discussed in Thread: LMK04832 ,
Hi,
I have verifying a design that includes the LMK04832 device. I am trying to assert the RESET to the LMK04832, but it doesnot generate the reset event. The schematic snippets of the…