Other Parts Discussed in Thread: LMK04906 I am wondering if there is a way round some of the limitations on the external VCO settings in the WEBENCH page for clock design. I am trying to model an LMK04906 driving a 10MHz OCXO in the PLL1 loop. The first…
Other Parts Discussed in Thread: DAC34SH84 , LMK04906 , LMX2581 , LMK01000 We are in the process of testing our dac circuit board design built with a DAC34SH84. We have confirmed our power supplies, confirmed we have read/write access to the registers…
Hi Grant,
As far as syncing two LMK04xxx parts, the latency from SYNC input to VCO output is not undefined. Per the LMK04800 datasheet: “Due to the speed of the clock distribution path (as fast as ~325 ps period) and the slow slew rate of the SYNC,…
Other Parts Discussed in Thread: LMK04906 , LMK03806 I down loaded the attached IBIS model from TI for the LMK04906 and noticed that although it is named after the LMK04906 the pinouts it contains pinouts for the LMK03806. Was this an error on TIs part…
You may consider using LMK04906 (6-output dual loop jitter cleaner/clock gen) configured for Single Loop mode (PLL2+integrated VCO). You can use Clock Design Tool to enter a model of your input clock phase noise and simulate the output clock phase noise…
Hello Lucas,
To date, none of the LMK devices support EEPROM/Non-volatile memory. Our devices to date include:
LMK010x0
LMK01801
LMK0200x
LMK030xx
LMK03200
LMK03806
LMK040xx
LMK041xx
LMK048xx
LMK04906
73,
Timothy
Other Parts Discussed in Thread: LMK03806 , LMK04906 I want to use LMK03806 in RRH solution.
At power on, PLL should be operate in free running mode and will be locking to SerDes recovery clock.
Can LMK03806 output clock be operating on free running…
Hello Stefano and Timothy,
This post from Timothy was very ineresting for me.
I would like to do an application with the LMK04906, but there are no information in the datasheet about the temperature dependencies if I use digital and analog delay…
You might consider LMK04906 which is a dual-loop jitter cleaner/clock generator with 6 DIFF outputs and capable of 100 fs rms jitter.
You can try to download/install CLOCKDESIGNTOOL to assist with device selection (LMK/LMX family of PLL devices), frequency…
Other Parts Discussed in Thread: LMK00301 , LMK04100 , LMK04906 , LMK03002 , LMK04806 , CDCE62005 , CDCM6208 I'm looking for a clocking solution:
Requirements:
Two 10 MHz reference inputs (LVTTL single ended) with input select signal.
Output 100…
