Part Number: LMK1D2102 Tool/software: Hello Experts,
Our design intends to use LMK1D2102. One input would be used for sysref 1.92MHz and another one for ADC refclk of 245.76MHz.
What is the single ended peak to peak range needed for LVDS input of…
Part Number: LMK1D2102 Tool/software: Hello Experts, What is the minimum single ended peak to peak LVDS level supported by LMK1D2102?
Will it support 245.76MHz LVDS 100mV pp single ended signal on P line and same signal on N line?
Can i get the Pspice…
Part Number: LMK1D2102 Tool/software: Hello,
1) I will have a CMOS clock input signal from a SMA connector connecting to pin IN0+, should I float pin IN0- ?
2) I only use the OUT0 LVDS output and other 3 outputs are unused, should I float EN pin?…
Part Number: LMK1D2102 Tool/software: Good day. I am designing a main board PCB for a test bench, and I have a question regarding the LMK1D2102RGTR:
Can I control the enable signal from an ADIO PXIe instrument the way I show you in the attached image…
Part Number: LMK1D2102 Tool/software: A few questions:
1. For the LMK1D2102RGTR, if I am only utilizing the IN0 Bus is it okay to leave the IN1 Bus floating or should this be grounded?
2. For the LMK1D2102RGTR, we plan to either use 3 or 4 output…
Part Number: LMK1D2102 Other Parts Discussed in Thread: LMK1D1208 Tool/software: Hi there,
LMK1D2102 datasheet table 9-1 "Output Control Table" states that when EN is 0: Clock Outputs All outputs disabled (static "0")
Is this saying that literally…
Part Number: LMK1D2102 Tool/software: Hello,
At DigiKey we received the LMK1D2102RGTT reel and product states MSL on package and has the correct bag but the datasheet states that these are MSL 1. Can you confirm what the MSL level is for the LMK1D2102RGTT…
Part Number: LMK1D2102 Other Parts Discussed in Thread: CDCLVD2102 , Hi staff
I am currently using CDCLVD2102. I plan to replace it with the updated version of LMK1D2102, but are there any issues that I should be aware of?
Users expect that the LMK1D2102…
Part Number: LMK1D2102 Hello team,
What is the input slew rate for differential clock input? I could only find slew rate requirement for single-ended input, which is 0.05V/ns (MIN).
Is there any jitter performance vs input clock slew rate data? I…
Part Number: LMK1D2102 Tool/software: Dear Team,
We are searching for the Fanout Buffer (10 MHz) which accepts the Single Ended 50 Ohm Sine Wave Input OCXO and covert it to square wave LVDS reference clock.
We are planning to use the LVDS buffer LMK1D2102R…
