Part Number: LMK6D Hi TI Team,
Qualification summary data is not available on TI.com.
Material name : LMK6DA05184ADLER
Could you provide me with the materials?
・Qualification summary
・Latch up Data
Best regards, Sakamoto/TED
Part Number: LMK6D Other Parts Discussed in Thread: LMK6C , Hi,
LMK6C (CMOS) specification is under condition on adding 2.2pF capacitor. How about LMK6D (LVDS)?? What is output load capacitor on LMK6D (LVDS) devices?
I understand LMK6D (LVDS) specification…
Part Number: TMS320F28P659DK-Q1 Other Parts Discussed in Thread: LMK6C , LMK6D Tool/software: Hello,
We will use the TMS320F28P659DK-Q1 microcontroller and I'm interested to use a low, the lowest jitter clock. I think about the LMK6 series who exists…
Part Number: LMK00308 Other Parts Discussed in Thread: LMK03328 , LMK6D Tool/software: Hi experts, I have a question regard the INPUT CLOCK of LMK00308.
I am using 100MHz oscillator which will supply the PLL LMK03328. This finally supply the 2ch CLOCK BUFFER…
Part Number: CDCE421A Other Parts Discussed in Thread: LMK6H , LMK6P , LMK6D , LMK3H0102 , I want to generate 48MHz differential clock. Kindly let me know how to do programming and what value need to set during programming through SDATA.
What is the meaning…
Hi Prasad,
The LMK6DA100000BDLE variant hasn't been released yet, but the other LMK6D variants can be found on the Material Content Search here: https://www.ti.com/materialcontent/en/search?partType=tiPartNumber&partNumber=LMK6D
All frequency variants…
Other Parts Discussed in Thread: LMK6D I'd like to use the "Load Data" feature under the Input Source (OSC) Noise. Do you have an example file for this and instructions on creating this data?
Part Number: LMK6C Other Parts Discussed in Thread: LMK6P , LMK6D , , LMK05318B Hello expert,
could we implement interleaved 180 degree clock signal to parallel PWM controller with 300kHz fsw?
Best regards,
Ann Lien
Part Number: ADC12QJ1600EVM Tool/software: Hello Eric,
Following your answer about the jitter of the clock driver chips,
what is the allowed CLK jitter on the ADC clock input which will not cause the Serdes at 12.375Gbps to loose lock?
Regards,
Giora