Part Number: LMX2492 I have been using this part in a design for quite some time, there has always been an interesting relationship in the CP settings and how it affects the loop bandwidth. As you increase the CP settings it does move the loop corner…
Part Number: LMX2492-Q1 Hello,
I am trying to determine if I can operate this component in the desired mode (FSK triggered by digital pin). Nominal Frequency 2200MHz, modulate at 10MHz, with a frequency deviation of 7MHz (0.7 Index). I would need a loop…
Part Number: LMX2492 Hi TI experts,
I'm looking for PLL chip featuring no internal VCO and minimun N divider value down to 1, and frequency range covers 2700MHz,do you have any suggestions?
thx!!
Part Number: LMX2492 Other Parts Discussed in Thread: LMX2595 We have noticed that if the SWRST bit is deasserted before programming the other registers the PLL does not lock ~1% of the time, but if it is only deasserted after the higher registers it seems…
Part Number: LMX2492 Hello,
I connected LMX2492 to an external VCO, and loop filtering adopted the fourth-order passive form. The simulation control adopted the TiPLLatinum and TICS Pro provided by Ti, in which the phase margin was set at 49.7° and the…
Part Number: LMX2492 Hi team,
The customer use LMX2492 + CHC2442 to generate 24G source signal, originally, 40MHz TCXO feeding to LMX2492, they works well for 24GHz source signal generation. However, when switching to 100MHz VCXO feeding to LMX2492, they could not functionally be ope…
Part Number: LMX2492 Hi Team,
The frequency synthesizer configuration is LMX2492+CHC2442, generating a Chirp signal with a time interval of 204us and a bandwidth of 50MHz. Our concern is that within the 204us duration, we need to traverse the entire 50MHz bandwidth. Does the LMX2492 need …
Part Number: LMX2492 Other Parts Discussed in Thread: PLLATINUMSIM-SW , LMX2594 Hi Team,
For Chirp signal genenrated by LMX2492+CHC2442, frequency .vs. time Chirp Linearity is critical for our application. However, Suggested by some experience, the actul generated Chirp Linea…
Part Number: LMX2492 Hello,
I am using PFD_DLY = 1 and the performace in good, but Is good idea set PFD_DLY=0 (Reserved) to reduce (a bit) the pull-in time?
What means PFD_DLY=0?
Thank you in advance
Part Number: LMX2492 Hi Team,
Good day. Can you please help with the inquiry below?
A customer use LMX2492 + CHC2442 to generate 24G source signal, originally, 40MHz TCXO feeding to LMX2492, works well for 24GHz source signal generation. However, when …