Part Number: LMX2572 I want too generate Ramp of 100 MHz with VCO free calibration and want to see this ramp in PLLatiunm Tool.
my PLL is getting locked but i am unable to see the ramp in the tool. please provide me guidance to generate a ramp.
Part Number: LMX2572 I am using PLLatinum Sim software for generating RAMP of 500 MHz in less then 20usec but i am not getting the option for setting ramp size please help.or share any video link if possible
Part Number: LMX2572 Hello
I just want to confirm the technical solution with you since you are the experts.
Due to ppm stability ( +-25 ppm ) I have decided to go with LMK6210-100M, this device have HCSL output freq.
From my understanding the HCSL…
Part Number: LMX2572 Hi There,
question, without resorting to buying an eval board.... at an output frequency near 340 MHz, (I am happy with whatever you have on file from 300 to 600 MHz) being an INTEGER multiple of the reference frequency (so that…
Hello Vincente,
We might configure the FSK wrongly. First thing we do is to configure the PLL with the carrier frequency on the PLL panel of TICS-Pro. You can see a screenshot of this panel below: Then we configure the FSK Mode using the "FSK" part of…
Hello Noel
This is a good question. We have produced 3 prototypes in this first small batch. Yesterday we performed the freq. jump test ( 1010-1015MHz) on the 3rd board and it looks like it is working without any fail to lock.
This means 2 boards of…
Part Number: LMX2572 Other Parts Discussed in Thread: LMX2581
Hello, this is a follow-up question to this: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1278540/trf3765-getting-phase-coherent-behavior-of-multiple…