Part Number: SN65DSI86-Q1
Tool/software:
Hi,
We use this device to drive display through display port cable. We are using semi-auto link training and noticed that device uses always default voltage swing(0) and Pre-emphasis(0) values even we try to add…
Part Number: SN65DSI86-Q1 Other Parts Discussed in Thread: TEST2 , SN65DSI86 Tool/software: Hi Team,
We're testing the color bar on SN65DSI86-Q1 and facing some issue, we can't get the output to display.
below "2DP_4DSI_RBR_800x600_Color_Bar.xml…
Part Number: SN65DSI86-Q1 Other Parts Discussed in Thread: SN65DSI86 , TEST2 Tool/software: Hi Ti teams,
We use SN65DSI86 to display color bar pattern,but only black display. The value of register 0x96 is 0x00, and the value of register 0xF8 is 0x12. The…
Hi Nikita,
It looks like 1080p at 60FPS is currently having issues, but we have an experimental setting for 1080p at around 30~40FPS. Would that be fine for your use case for now?
Regards,
Takuma
Part Number: SN65DSI86-Q1 Hi TI teams,
The eDP lane assignment and lane polarity can be configured at the same time through 0x59 and 0x5A register. The connection is showed as below. Is it correct ？
Part Number: SN65DSI86-Q1 Other Parts Discussed in Thread: SN65DSI86 , TEST2 The following error occurs when imx8mm is used for SN65DSI86, Linux5.10
ti_sn65dsi86 3-002d: [drm:ti_sn_bridge_enable] *ERROR* Link training failed, link is off (-5)
This is my…
Part Number: SN65DSI86-Q1 I 'm going to select the part for MIPI to eDP
The LCD to be used has the following specifications.
-. 3840x2160 resoluton, eDP 1.4 interface, 10bit Color Depth, min 350nit @SDR, HDR1000
so. I want an IC that supports the features…
Part Number: SN65DSI86-Q1 Other Parts Discussed in Thread: SN65DSI86 , SN65DSI83 Hi TI,
I have a question about pixel clock in SN65DSI86.
I want to input 16.5MHz as the pixel clock and output 8.25MHz. Is this possible?
If possible, where should I set…
Part Number: SN65DSI86-Q1 Other Parts Discussed in Thread: SN65DSI86 Hi Team,
Using SN65DSI86 to implement a DSI-to-DP signal to illuminate the screen.
4 lane of DSIA is being used, DP lanes is 2 lane, external clock is used by refclk which is 19.2MHz. The…
