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Showing 6 results View by: Thread Post Sort by
  • RE: TPL5010: Reset why?

    Michael Srinivasan
    Michael Srinivasan
    Hi Nathalie, I went into lab to try to replicate this. I used the TPL5010EVM. I have attached the oscilloscope capture below. As you can tell, I am manually issuing several DONE pulses (purple waveform) to the device during each interval, but the…
    • 7 months ago
    • Clock & timing
    • Clock & timing forum
  • RE: TPL5010: WAKE is toggling sometimes while DONE is tied to GND

    Lane Boyd
    Lane Boyd
    Hi Jason, Can you send me your oscilloscope capture of the WAKE, RSTn, and DONE waveforms? This may shed some light into what is causing the WAKE pulses. In my setup I am using the TPL5010EVM powered by a coin cell battery and DONE is pulled to…
    • over 7 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: TPL5010: Reset signals completely disabled after a certain condition

    Lane Boyd
    Lane Boyd
    Resolved
    Hi Nizar, I wasn't able to replicate your issue on my bench using TPL5010EVM. In my setup: VDD = 5V R_ext = 500ohm => T_ip = 100ms DONE pin is pulled down to ground With this setup, RSTn will be periodic; RSTn will remain high for 100ms…
    • over 7 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: TPL5010: What happens when DELAY/M_RST is held indefinitely

    Lane Boyd
    Lane Boyd
    Hi Henry, I tested this on the TPL5010EVM with CR2032 battery. If VDD is connected to DELAY/M_RST indefinitely, RSTn will be pulled to GND indefinitely. Also, it is not recommended to pull DELAY/M_RST to VDD during startup. After POR, the device…
    • over 7 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: TPL5010: power-on-reset and supply rise time limitation

    Lane Boyd
    Lane Boyd
    Hi Hong, Thanks for providing your oscilloscope waveforms. They are very helpful for me because I still am not able to replicate your issue. Can you confirm that you are testing on the TPL5010EVM? Or are you using another board? Q5: Can you give…
    • over 7 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: TPL5010: What is the minimum rising slope of VDD that will lead to power on reset

    HONG GAO2
    HONG GAO2
    Dear Lane, Thank you for your reply. My test bench is attached. I used two current sources to supply 300uA to two 47uF capacitors and limited the voltages of current sources to be 2.1V and 2.9V seperately. So the two 47uF can be regarded as two…
    • over 7 years ago
    • Clock & timing
    • Clock & timing forum

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