Hi
The ADC12D500RF has a minimum clock rate of 150 MHz in non-DES mode and 200 MHz in DES mode. The different lower limit for DES mode is due to the duty cycle stabilization circuitry used in that mode.
The 150 MHz limit is required to ensure that…
Archie,
For #1: See attached document.
For #2: The board is designed to use the HPC on the FPGA platforms.
For #3: You can use the source code that can be found under the TSW14J10EVM product folder (older Xilinx code that is not recommended) or…
I am using TSW12J54EVM and TSW14J56EVM to acquire pulsed data output from a photo-multiplier tube.
However we got some really strange trigger behavior when we configured the system following the defaults outlined in the manual.
In our setup we had…
Hi Jani
The LMK04828 is included to provide flexible support for the JESD204B SYSREF and FPGA Device Clock requirements of the system. The FPGA requires 1 or 2 clocks in addition to the JESD204B SYSREF. The ADC requires a device clock and also needs…
Hi new2day
There are usually a number of possible configurations for synchronizing multiple ADCs.
Unfortunately synchronizing multiple ADC12J4000 with Fclk at 4000 MHz is tricky since the divided down SYSREF and FPGA clocks from each LMK04828 cannot…
I am using the ADC12J4000EVM together with the TSW14J56EVM . The SW I use is High Speed Data converter Pro 2.6, together with the ADC12J400EVM GUI version 1.3
I would like to decimate the samples. I configure both the ADC and the TSW with the same decimation…
Other Parts Discussed in Thread: TIDA-00467 , LMK04828 , DAC38J84 Hi,
I am building a mmWave system evaluation platform. I will be using V|E-band transceivers with analog BB/IF differential IQ ports interfacing the DAC/ADC boards. In order to generate…
Josh,
The data rate will be 1Gsps but this data consists of both I and Q data. If you were to process the FFT, you would use a complex FFT to show both negative and positive frequencies. This bandwidth would then be -500MHz to +500MHz. See figure 3…
Other Parts Discussed in Thread: ADC12J4000 , ADC16DX370 , LM15851 Hello.
I want to ask about real time streaming and saving data system.
The product which i saw is like this :
ADC12J4000 Evaluation Module : http://www.ti.com/tool/adc12j4000evm…
Hi Timothy,
Thank you for your documents. I think the LMK chip might be damaged, and that might be the reason it doesn't output correct frequencies. So I decided to continue my experiments on the LMK04828 and LMX2581 from ADC12J4000EVM, since on this…
