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Showing 104 results View by: Thread Post Sort by
    Answered
  • RE: Differential clock buffer which supports SSTL, HSTL, and POD interface

    Alan O
    Alan O
    Resolved
    You can use LVPECL buffer (LMK00301/30x, CDCLVP1204/12xx) and level-translate to interface to HSTL inputs. See Figure 8 in this app note: www.ti.com/.../scaa059c.pdf Alan
    • over 9 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • LMX2582: Need to output 2GHZ and 4GHZ for LMX2582

    Mickey Zhang
    Mickey Zhang
    Resolved
    Part Number: LMX2582 Other Parts Discussed in Thread: CDCLVP1204 , CDCLVC1103 Hi team, The customer would like to use CDCLVP1204 + LMX2582. The input frequency is 100MHZ. He needs to output 100MHZ, 2GHZ and 4GHZ. The output frequency 100MHZ is used…
    • Resolved
    • over 7 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: Regarding CDCLVP1204RGTT output

    Arvind Sridhar
    Arvind Sridhar
    Resolved
    Hi Amit, From the CDCLVP1204 datasheet, max VOH = Vcc-0.9 V and min VOL = Vcc-1.7 V. This gives a maximum single ended swing of 0.8V. The unused output can be terminated as explained earlier. It should be possible to AC couple the single ended output…
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: CDCLVP1204RGTR thermal resistance

    Arvind Sridhar
    Arvind Sridhar
    Hi Hori-San, We have the following thermal data for CDCLVP1204. Theta JA-High K (standard datasheet value) 51.8 Theta JC, top (standard datasheet value) 79 Theta JB (standard datasheet value) 20 Psi JT …
    • over 10 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: CDCLVP1102: CDCLVP1102 does not have the output signal

    Tim Chao Li
    Tim Chao Li
    Resolved
    Hi Mickey, 1. Yes, Vac_ref can be left floating if unused. 2. The difference between these parts is as follows. See also the block diagram in the respective datasheets. CDCLVP1102: 1:2 LVPECL buffer CDCLVP2102: 2x 1:2 LVPECL buffer (it is like having…
    • over 8 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: CDCLVP1102 - Can this take an HCSL signal on the input pin and output an LVPECL signal?

    Alan O
    Alan O
    Resolved
    Brian, HCSL driver interface to DIFF input of CDCLVP1102. The double termination attenuates the HCSL swing in half to stay within the differential input swing specifications. Rb resistors are used to bias the AC coupled inputs within the input common…
    • over 9 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: LMK61E2 - Schematic assistance

    Tim Chao Li
    Tim Chao Li
    Hi Waqas, The resistors are necessary for terminating the oscillator's LVPECL output by biasing the internal transistors and cannot be omitted unless the receiver features internal termination at its input. The capacitors are used to AC couple the…
    • over 9 years ago
    • Clock & timing
    • Clock & timing forum
  • AFE5808 Clock Input

    Mehdi Tamehi
    Mehdi Tamehi
    Other Parts Discussed in Thread: AFE5808 , CDCLVD1204 , CDCLVP1204 The AFE5808 datasheet talks about compatible LVDS clock inputs: >AFE5808 page 61 has the LVDS wiring configuration >AFE5808 page 11 "ADC INPUT CLOCK" says LVDS "Typ" Vpp=0.7V …
    • over 11 years ago
    • Data converters
    • Data converters forum
  • Answered
  • RE: 40 MHz clock for a receiver

    Arvind Sridhar
    Arvind Sridhar
    Resolved
    Hi Omid, What is the preffered output type for the reference clock - Single ended or differential? We have an 5X7 oscillator family in the design pipeline (Samples April 2015) that can support this frequency with different flavors of output drivers…
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • Where to place Termination: AC coupled LVPECL CDCLVP1102

    Alfred Key
    Alfred Key
    Resolved
    Other Parts Discussed in Thread: CDCLVP1204 , CDCLVP1102 I am using the CDCLVP1102 (same family as the CDCLVP1204) to drive PCIexpress 100MHz reference to the input clock pins of Xilinx Virtex6 device. I have two questions: Where should I locate…
    • Resolved
    • over 14 years ago
    • Clock & timing
    • Clock & timing forum
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