Part Number: CDCM7005 Hi Team, I saw abnormal charge pump voltage scope like as below.
PDF is 80kHz and matched with scope peak period. When I measured in EVM, CP voltage scope was different.
In my understand, CP voltage level should be stable…
Part Number: CDCM7005 We want to use CDCM7005 to improve clock jitter. The evaluation board (CDCM7005-SP Evaluation Module) is configured to work with PECL VCOs although we plan to use LVCMOS 100 MHz VCXO. The board is populated with PECL terminating…
Part Number: CDCM7005-SP Hello All,
at www.ti.com/radiation I cannot find SEE test report on CDCM7005-SP (5962-0723001VXC). How can I have it?
Best regards,
Dmitry
Part Number: CDCM7005 Other Parts Discussed in Thread: LMK05028 Hello,
I am trying to develop a solution that will take a 10 MHz signal from a OCXO and synchronize it to a 1PPS signal from GPS. Afterwards, I would like to synthesize frequencies that…
Part Number: CDCM7005EVM-CVAL Other Parts Discussed in Thread: CDCM7005-SP Hello,
I have the 2018 release of CDCM7005-SP EVM GUI. What is the correct adapter cable to connect to SPI interface of the eval board?
thanks,
Miles
Part Number: CDCM7005-SP We are currently involved into the development of flight hardware for an European ESA mission. We foresee to implement a jitter cleaner based on the CDCM7005-SP PLL controller. ESA is asking for a flight heritage of this device…
Other Parts Discussed in Thread: CDCM7005 Hello,
I am unable to have a lock on the clock while having a reference 48Mhz clock and a 48Mhz output.
I am using the passive loop capacitors and resistor values that are given as example in the datasheet…
Hi Tim,
I monitor the pins:
- PRI_SEC_CLK (23 qfn) to know the reference clock selected
- PLL_LOCK (25 qfn) to know if the PLL is locked
In automatic mode (word_0, bit_30 = 1), the PRIM_CLK is selected and if I remove it, the CDCM doesn't toggle…
Other Parts Discussed in Thread: CDCM7005 Hello,
While using a custome prototype board. I am unable to have a lock on the clock while having a reference 48Mhz clock and a 48Mhz output unless I am using Cycle Slip Lock Window. However it doesn't seem…