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Showing 291 results View by: Thread Post Sort by
  • CDCM7005 PLL FILTER design

    Sara Caron76
    Sara Caron76
    TI Thinks Resolved
    Other Parts Discussed in Thread: CDCM7005 Hi I have TI's Excel spreadsheet PLL Calculations.xls to help me calculate Loop filter parameters. When I input the following: Fc=1.2GHz P=10 N=12 M=1 Fref = 10 MHz Ko=70 kHz/V I get an analyzed…
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: CDCM7005-sp phase noise question

    SWalter
    SWalter
    Resolved
    Dave, Following screenshot shows the typical 1GHz input and output (LVPECL) signal of CDCM7005. (This is captured in buffer mode only. Input source is a signal generator and not capable to run in PLL mode.) Till 300k the output performance follows the…
    • over 10 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • CDCM7005-sp DC power requirements

    Sara Caron76
    Sara Caron76
    Resolved
    Hi From analysis done before I cam to design with this product I am looking at 420 mA at 3.3V for the part. How much is used by the Analog section. I am trying to size and procure a ferrite bead to clean up the Analog section. Thanks
    • Resolved
    • over 10 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: CDCM7005 - LVDS signal capability to VCXO_IN

    Julian Hagedorn
    Julian Hagedorn
    Resolved
    Hello Kawai-san, the CDCM7005 VCXO input does accept very small swings down to 100mV differential. If you can do AC coupling plus biasing you can connect LVDS directly to VCXO_IN. Best regards, Julian
    • over 10 years ago
    • Clock & timing
    • Clock & timing forum
  • CDCM7005 LVPECL ouput swing too large

    Arhippa Kovanen
    Arhippa Kovanen
    TI Thinks Resolved
    Other Parts Discussed in Thread: CDCM7005 Hi, The LVPECL output swing of the CDCM7005 is too large. I measure 1.5 V from one branch i.e. differentially 3 Vpp. Standard is 0.8 V. Is there settings which affect the swing? The outputs are AC coupled. Before…
    • over 10 years ago
    • Clock & timing
    • Clock & timing forum
  • CDCM7005-SP Assembly Question

    David Durachka
    David Durachka
    TI Thinks Resolved
    Other Parts Discussed in Thread: CDCM7005-SP Good morning, Should the thermal pad on the CDCM7005-sp be soldered to the pad under the part? I see very good guidance for the part assembly for the non-flight version of this part, but haven't seen anything…
    • over 10 years ago
    • Space & High Reliability (Read Only)
    • Space & High Reliability Forum (Read Only)
  • Is it ok to swap the VCXO_IN and VCXO_IN_NOT inputs to the CDCM7005?

    Todd Reed
    Todd Reed
    TI Thinks Resolved
    I want to switch oscillators due to footprint, but the new oscillator has the differential plus and minus swapped. Would this just invert the output from the 7005? Thanks, Todd
    • over 9 years ago
    • Clock & timing
    • Clock & timing forum
  • cdcm7005-sp programming

    Sara Caron76
    Sara Caron76
    Hi I have the spreadsheet for choosing the loop filter components. I am using the passive loop filter topology. When I look at the datasheet Word 0 asks for the divider M and N (which I guess is P from the spreadsheet). Is this correct? My Fref…
    • over 10 years ago
    • Clock & timing
    • Clock & timing forum
  • CDCM7005 Lock and Unlock

    Jin Kyung Han
    Jin Kyung Han
    Other Parts Discussed in Thread: CDCM7005 , CDCM7005-SP 4111.CDCM7005.zip Hello I wold like to ask you to review the below M y cusotmer is testing CDCM7005 and she is facing with PLL Unlock problem and the below are staus for setting values. What…
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: CDCM7005 - Active loop filter design

    Kawai
    Kawai
    Resolved
    Thank you, Gabe-san。 Best Regards, Kawai
    • over 11 years ago
    • Clock & timing
    • Clock & timing forum
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