Other Parts Discussed in Thread: LMK04826 Hi,
We have some questions about LMK04826 JESD204B operation.
Q1
tsJESD204B equals ‐80ps(TYP) in the datasheet. What does the spec mean ?
I believe the rising edge of the SYSREF needs to be valid before…
Other Parts Discussed in Thread: LMK04826 Hi,
Our customer is looking for clock devices that suport JESD204B.
I will propose LMK04826/28.
So,is there a competitive analysis list in JESD204B specification?
Best Regards,
Kato
Other Parts Discussed in Thread: LMK04826 Hello,
When I try to open previous LMK04826 WebBench Designs saved under my Login, the WebBench App opens but won't load any designs. It pops up a box that says "Project Not Available".
My designs are a little…
Hi Kato-San,
Please follow the general recommendations shown in the user guide for LMK04826.
http://www.ti.com/lit/ug/snau145a/snau145a.pdf
Regards
Arvind Sridhar
Other Parts Discussed in Thread: LMK04826 Hi,
Our customer is considering LMK04826 for JESD204B Compliant clock.
However, there is some possibility that their system is required 9 Differential Device Clocks and 9 SYSREF Clocks.
LMK04826 is configurable…
Hello,
I posted the following question earlier today in the "Clock and Timing" forum, but this may be a better forum to post it:
When I try to open previous LMK04826 WebBench Designs saved under my Login, the WebBench App opens but won't load any…
Hi,
I have a question about PLL1_LD_MUX function.
Regarding SPI Readback, DAC Low/High, PLL*_N, PLL*_N/2, PLL*_R and PLL*_R/2, please let me know how to monitor for PLL1 LD pin.
Best Regards,
Kato
Hi,
Customer would like to know about holdover.
Could holdover setting for pin select mode take the place of holdover force mode 0x14[3] ?
Best Regards,
Kato
