Part Number: LMK61E2 hi Expert
Here, I see that the default values of the R16 and R17 registers are 0x00 and 0x80 respectively, but why do I read them out as 0x00 and 0x88 at the beginning
When I adjust the frequency offset, apart from configuring…
Part Number: LMK61E2 Other Parts Discussed in Thread: USB2ANY Writing directly in the registers with an I2C interface was easy using TICS pro only for generating right configuration and then writing registers the oscilator was working properly from 156…
Part Number: LMK61E2 Other Parts Discussed in Thread: USB2ANY , Tool/software: Hi, TI expert.
There is an inquiry from a my customer regarding LMK61E2.
[Question]
Although control was performed based on the datasheet, there is no change in clock…
Part Number: LMK61E2 Other Parts Discussed in Thread: LMK03318 Tool/software: Hello.
I have a question about presence of shadows registers for >8 bits settings.
It is common practice to implement such registers when the stored value exceeds 8 bits…
Part Number: LMK61E2 Other Parts Discussed in Thread: LMK61E0M Tool/software: Hi,
Datasheet of LMK61E2 (SNAS674B – SEPTEMBER 2015 – REVISED FEBRUARY 2017) states in Pin function table: ' When left open, LSB of I2C slave address is set to 01. When tied…
Part Number: LMK61E2 Other Parts Discussed in Thread: AFE7953 Tool/software: Hi Team,
Can the LMK61E2 generate a 491.52MHz reference clock for a radar system using AFE7953?
Best,
Jason
Part Number: ADC12DJ5200RFEVM Other Parts Discussed in Thread: LMK61E2 Tool/software: Hi,
I am using evaluation board ADC12DJ5200RFEVM with ADCxxDJxx00RF EVM GUI.
Initially, the LMK61E2 chip was successfully configured using the ADCxxDJxx00RF EVM…
Part Number: ADC12DJ5200RFEVM Other Parts Discussed in Thread: LMK61E2 , Tool/software: Hello, Using ADC12DJ5200RFEVM GUI, my customer programed the LMK61E2 registers to match a desired setting first. Then, they must have written a 1 to R49.6 so that…
Part Number: LMK61E2 Hi Team,
Customer wants to check how many cycles we can support for LMK61E2 NVM memory? We see there is one R48 register to indicate the Erase/Program cycles, which is one byte 255 cycles. Does this mean only 255 cycles supported…