Other Parts Discussed in Thread: TUSB1210 Hi,
I have a problem with MUSB solution on my board using TUSB1210 chip. When plugging in a flashdrive I expect to get some power out of the USB-M connector but it remains inactive and nothing is being detected…
Can team share customer how to perform electrical testing on TUSB1210?
The customer is using linux OS. I found the the USB HS/LS PHY testing procedure are base on WINDOWS system. There is no Linux base testing procedure. Do we have experience share…
Other Parts Discussed in Thread: TPS65920 , DM3730 , TUSB1210 HI
We have problems in debugging arm USB communication at present, when the device is powered up or reset, the link is not find the lna9513.
We use the following:
DM3730.usb0…
Hi,
Question about using TUSB1210 with AM3505. Seems that the device has been detected all right,
[ 0.165344] musb-hdrc: version 6.0, host, debug=0 [ 0.165679] musb-hdrc musb-hdrc.0: degrade from otg to host-only mode [ 0.165740] musb-hdrc musb-hdrc…
Other Parts Discussed in Thread: TUSB1210 In our design (based on OMAP3630 and TUSB1210), the only usb device connected to TUSB1210 is an on-board wcdma modem module, which is separately powered.
Now I know the ID pin should be tied to ground, but I…
Other Parts Discussed in Thread: TUSB1210 Hello,
We are going to use the TUSB1210 in our design, but we are curious what the tradeoffs are for powering the Vdd33 pin from the internal source and an external source? Is there a potential power savings…
John,
ID pin is used to determine of the TUSB1210 is in host or peripheral mode. In OTG applications, this is handled by the cable. For permanent host applications, then ID must be grounded.
The VBUS pin of the TUSB1210 is not needed in stand…
Other Parts Discussed in Thread: TUSB1210 , TUSB1211 I would like to clarify the VBUS, ID and REFCLK settings shown in Figures 10.1 and 10.2 in the TUSB1210 data sheet.
http://www.ti.com/lit/ds/symlink/tusb1210.pdf
In Figure 10-1 (Host or OTG…
Rajesh,
We do not have a Verilog model available. The TUSB1210 meets the defined ULPI timing requirements. As long as your core meets the timing requirements, there should be no interoperability issues.
On page 15 of the datasheet there is a timing diagram for power up in ULPI clock input mode. I don’t see a table for power up timing in ULPI clock output mode. We are using the PHY in clock output mode and noticed that we don’t get a clock out without…
