LPV812: Offset matching

Tnx, I understand the point.

I am not a low-level chip designer, so I do not know what the root causes of e.g. an offset are.

I was assuming that process variations may cause it.

Practically thinking a misalignment of masks in the manufacturing process may cause it.

But then though local, the effect on the second OPAMP on the other end of the chip may still be correlated - same mask misalignment (even with a stepper).

How local are the effects that cause an offset?

I have difficulty to imagine such narrow causes.

On the other hand I can imagine contributions to offset that are correlated across the die e.g. temperature.

Anyway: The argument is clear, is it also empirically verified i.e. measured?

Is there really no significant correlation?

In another thread I read that variation (of e.g. AOL) can go down to 1% across the same wafer. 

It surprises me that offset should be THAT local.

Mask misalignment would affect both transistors in nearly the same way, so it would not generate much of an offset.

As far as I know, local variations are caused by impurities in the silicon, and variations in the chemicals used when etching. The differences are smaller in nearby areas.

Placing the two input transistors near each other is so important that some opamps use multiple transistors in parallel for each input and interleave them, so that local variations affect a similar number of transistors of each input. For example, the OPA627 has eight transistors per input, in a 4x4 pattern:

^{(source: www.richis-lab.de/Opamp22.htm)}

As Clemens said, there is absolutely no correlation between offsets or IB's (in CMOS) of two channels on the same chip because ALL variations on a good layout are caused by wafer fab process under and/or over-etching of diffusions.  This is, however, not the case with misalignment of masks because then the offsets of both channels would be shifted in one direction (a systematic error) and result in both channels having "matching" away from zero. In general, all specs centered around zero have no correlation because the only reason for them not being zero are controlled by the physical limitation (resolution) of the lithographic process used to manufacture ICs.  For this reason they are random in nature and thus follow Normal Gaussian distribution centered around zero.

Having said that, in case of bipolar input transistor op amps with no IB cancellation, IB's of both inputs (or channels) flow into input terminals for npn and out for pnp - in such case there is matching within 10% (bipolar transistor variation of beta) because IB's in such case are not centered around zero.