• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 50 subscribers
  • Views 218 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV9102: Output Oscillation issue with CL

ttd
Mastermind 7730 points
Part Number: TLV9102
Other Parts Discussed in Thread: ADS8862,

Dear Technical Support Team,

 

I have Output Oscillation issue with 2700pF on output.

The configuration is buffer for ADS8862.

When Riso is inserted on output, then output seems to be stable(No oscillation).

 See attached file.

4405.TLV9102_ADC.pdf

 

Q1

Could you provide two TINA TI simulation?

① Phase margin and stability when driving TLV9102 with CL=2700pF and Riso=0Ω

② Phase margin and stability when additionally inserting Riso=2.2kΩ with  CL=2700pF

Q2

 If you have more appropriate RC value for ADC driver, please could you share them?

 

P.S

ADS8862 datasheet shows  Charge-Kickback Filter and RFLT ≦22Ω and CFLT ≧590 pF(Figure 62. Charge-Kickback Filter), but my configuration is simply RC filter for ADC driver.

 

Best Regards,

ttd

  • 0
    TI__Genius 10450 points

    Hello, 

    We have references on TI Precision Labs to help show how to run TINA simulations for stability analysis: Spice Simulation

    There are also many other resources on op amp stability and minimizing oscillations referenced in this e2e post here for future reference. 

    Per your request, I have copied below the TINA simulations with the TLV9102 and the conditions provided: 

    ttd said:
    ① Phase margin and stability when driving TLV9102 with CL=2700pF and Riso=0Ω

    For the ease of simulation, I used a dual-supply configuration, but there will be no impact to the AC stability simulation results. As you can see, the phase margin is low for a 2700pF cap load without an Riso and is considered marginally stable. 

    ttd said:
    ② Phase margin and stability when additionally inserting Riso=2.2kΩ with  CL=2700pF

    The phase margin for this configuration is now above 45degrees which is considered stable. This is why the oscillations are no longer present. 

    ttd said:
    If you have more appropriate RC value for ADC driver, please could you share them?

    To select the appropriate RC values, we recommend to use the Analog Engineer's Calculator: https://www.ti.com/tool/ANALOG-ENGINEER-CALC

    You can input the ADC datasheet information in the calculator to then get the recommended RC filter values. Rfilt and Cfilt sets the RC filter for the ADC driver.

    Please let me know if you have further questions.
    Thank you!

    Best Regards,
    Ashley

  • 0 in reply to Ashley Kang
    Mastermind 7730 points

    Hi Ashley,

    Thank you for your quick reply and TINA TI simulation.

    I understand that ② has enough phase margin.

    Is it possible to attach TSC simulation files(① and ②)?

    Also I'd like to refer Analog Engineer's Calculator for RC filter values.

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Mastermind 18217 points

    Hey TTD, 

    Please see attached file here: TLV9102_Riso.TSC

    To see both scenarios just change the value of RISO. 

    All the best,
    Caro