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INA4181: About the internal block diagram and power consumption issues of INA4181

JH Zhang
Prodigy 210 points
Part Number: INA4181
Other Parts Discussed in Thread: INA186, INA2191, INA4290, INA280, INA281

Hi TI experts,
I was using INA4181A2IPWR and found that it has a large power consumption after shutting down. The test is as follows. IN+1 and IN-1 are directly connected to the power supply B+ through RSENSE. It has no MOS tube control and always supplies power to the INA4181A2IPWR input pin IN+1. and IN-1. When testing the system shutdown power, it was found that the IN+1 pin will cause a current of 75uA, which is unacceptable for my product design.
As shown in the attached specification picture, I connected REF to ground and disconnected it, but the 75uA current did not decrease.
So I want to know if the internal block diagram of the IN+1 pin of this INA4181A2IPWR is equivalent to connecting a 250KΩ resistor to ground? How is this IN+1 pin connected internally? I would like to refer to how to reduce power consumption, or do you have a better solution?

  • 0
    TI__Mastermind 32395 points

    Hello Appreciated Engineer,

    Thank you for posting your question. I am looking this over and will respond shortly.

    Sincerely,

    Peter

  • 0 in reply to Peter Iliya
    TI__Mastermind 32395 points

    Hello,

    Even with Vs=0V, the input bias currents can go to 75 µA per Figure 6-21 of datasheet.

    There is a path to GND pin from IN+ pin via the disabled output of internal op amp as mentioned in the text.

    There is also a path to GND from input via the input bias stage, which is not shown in the image you attached, but is elsewhere in datasheet (see below).

    This 75 µA input current is essentially unavoidable

    The only other option is to use the INA2191 or four INA186's.

    Sincerely,

    Peter

  • 0 in reply to Peter Iliya
    Prodigy 210 points

    Hi Peter,

    Thank you for your reply.
    There is another question. I only tested that IN+1 has a power consumption of 75uA, but IN-1 did not test the power consumption. Is my test result correct? If it's wrong, please correct it. If it's correct, can you analyze it from a block diagram perspective? According to my understanding, IN+1 and IN-1 are directly connected to Bus Voltage. Is this any different?

  • 0 in reply to JH Zhang
    TI__Mastermind 32395 points

    Hey JH,

    I think most of the current is flowing through IN+ because there is a path to ground as shown below in blue:

    However, it really does not matter because the only way to decrease current is to increase RF for both input pins IN+ and IN-. However, once RF>10-Ω, you will begin to add significant shunt voltage gain error to circuit (see section 8.1.3 of datasheet).

    You could also decrease power adding switches in series with IN+ and IN- to open up this pathway, but this will incur offset error due to differences in Vds, on voltage.

    Other than this, the only option is to use another device. Here are what I would recommend:

    1. The INA4290.
      1. This is the only other 4-channel device we have currently.
      2. IB < 2.5uA during shutdown (see Figure 6-14 of datasheet)
    2. Four INA280's. The INA280 is very similar to each channel of INA4290 with lesser accuracy, but better price.
      1. If you need device to operate on low-side (Vcm=0V), then use the INA281.
    3. Two INA2191. 
      1. Very low IB and IQ
    4. Four INA186
      1. Very low IB and IQ. Cost optimized.

    Sincerely,

    Peter

  • 0 in reply to Peter Iliya
    Prodigy 210 points

    Hi Peter，

    The devices you recommended are more expensive than the INA4181A2IPWR for four-channel sampling, which is not cost-effective.
    Also, I still want to know why only IN+1 has a power consumption of 75uA when my power supply is about 19V, but IN-1 is not affected? My test method is to disconnect the IN+1 and IN-1 power supply circuits successively. I found that only when IN+1 is disconnected, the 75uA power consumption is gone, while IN-1 has no effect on the power consumption. The path to the ground you described above is from IN-1 and then to the ground. This is contrary to my test conclusion.

  • 0 in reply to JH Zhang
    TI__Mastermind 32395 points

    Hey JH,

    Yes this is contrary. I should have shown some more complete diagrams.

    These three diagrams show shutdown input bias current pathways when REF = float and both inputs are connected and when only one input is connected. They all will yield the same total input bias current from your 19V bus because the bias circuit is ~2.5kΩ, thus when in parallel with the small shunt it creates a negligible current pathway.

    Here are the currents when REF is connected to GND. In this case, the total input bias current should double.

    You say that you disconnected IN+1 and IN-1 successively. Does this mean that you ever tested the device with IN+1 pin floating and IN-1 pin connected to 19V?

    What are the other input pins (from the 3 other channels) connected to the same bus as well?

    How are you disconnecting REF pin from ground?

    Maybe one way to decrease the input bias current to place a FET switch at GND pin; however, this is not usually recommended because rapidly shorting GND pin from float while other pins are biased to another voltage can create a potential latch up risk..

    Sincerely,

    Peter

  • 0 in reply to Peter Iliya
    Prodigy 210 points

    Hi Peter，

    "You say that you disconnected IN+1 and IN-1 successively. Does this mean that you ever tested the device with IN+1 pin floating and IN-1 pin connected to 19V?", yes, when I put IN+1 When the pin is disconnected and the IN-1 pin remains connected to the 19V power supply, the power consumption is less than 1uA. This is my actual measurement result.
    The other three channels cannot generate power consumption from the hardware schematic design and can be ignored.
    My current idea is to add a PMOS switch control to the IN+1 pin. When I shut down the computer, I can disconnect the IN+1 pin to the 19V power supply through PMOS, thereby reducing power consumption. Is this okay?

  • 0 in reply to JH Zhang
    TI__Mastermind 32395 points

    Hey JH,

    Sorry for delay from yesterday's holiday. I will respond promptly.

    Best,

    Peter

  • 0 in reply to Peter Iliya
    TI__Mastermind 32395 points

    Hey JH,

    You could open up IN+ pin to reduce overall power consumption. The disadvantage is that you will significantly increase offset error (make input offset, Vos, more negative) due to PMOS drain-to-source voltage.

    If you can calibrate out the offset voltage with a 1-point calibration, then you could negate this error. One-point offset calibrations are much easier if REF > 0V, so system can read Vout in linear range with load = off (as opposed to load = precise source).

    If you cannot do a 1-point calibration, then you could open both input pins with same PMOS so offset error is dominated by the variability in Vds of two PMOS FETs.

    Sincerely,

    Peter