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Hello,
We are interested in ULCD function of OPA994 for capacitive load drive use case.
GBW characteristics will be optimized from no capacitive load 25MHz full band to certain GBW depended on load capacitance.
Here is questions. In that case what is SR and maximum output current characteristics?
Even heavy capacitive load drive condition full voltage swing SR is keeping 35V/usec and +/-124mA output current will not degraded?
Regards,
Mochizuki
Hello Mochizuki-san,
I apologize as I don't fully understand the question. Are you asking what is the SR and max output current with no capacitive load present?
If I'm understanding the question, the answer the max output current will not change due to capacitive loading, or lack there of. SR might change over different cap loads however.
Best Regards,
Robert Clifton
Hi Robert,
I have meant when look at this phase margin characteristics, it is showing GBW is adjusting by the load capacitance.
For example what is SR and output current at 1uF load capacitor? Is it still keeping performance of 35V/usec and +/-125mA output current?
Regards,
Mochizuki
Hello Mochizuki-san,
It looks like we didn't collect that data. As I said the maximum output current shouldn't change but the slew rate might. Is there any other conditions besides a 1uF capacitive load that you are wanting to see what the slew rate looks like. For example:
Best Regards,
Robert Clifton
Hi Robert,
I brought up 1uF load was that one of example of the working condition in general.
In the market OPA994 ULCD is very useful for various load capacitance like long cable driver, the capacitance might be changed by length of a cable, the customer expects to see stable SR 35V/us ramp-up at any case from the datasheet speciation.
Can we see accurate SR simulation result on TINA-TI?
Regards,
Mochizuki
Hello Mochizuki-san
Today is a US holiday. Robert will get back to you tomorrow.
Hello Mochizuki-san,
I don't believe we guarantee that the slew rate will remain at 35 V/us under every capacitive load. I'll take a look into this and to see if this device also has slew boost.
Slew boost architecture will vary the slew rate depending on the differential voltage on the inputs.
This might take several days to hear back from the design team.
Best Regards,
Robert Clifton
Hello Mochizuki-san,
Thank you for your patience.
I got back with the design team and learned a few things.
Let me know if you have any additional questions.
Best Regards,
Robert Clifton
Hi Robert,
Thank you for the information.
It seems the device does not purpose to use high speed signal cable driver, motor driver or headphone driver even it has +/-125mA Io current.
But still it has benefit of very stable phase characteristics.
Can we see behavior of SR boost characteristics on TINA TI?
Regards,
Mochizuki
Hello Mochizuki-san,
For our models, we only model the higher slew rate, as in we model the device when slew boost is active. We don't model the transition between the natural slew rate to slew boost.
Best Regards,
Robert Clifton