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Original question:

LM117HVQML:LM117HVQML

LM117HVQML:LM117

HIROKAZU MONMA
Prodigy 40 points
Part Number: LM117HVQML

Tool/software:

Thank you for your help.

If the input frequency is between 1MHz and 400MHz, is it possible that the PSRR will fall below 10dB?

If it falls below 10dB, how far will it fall?

Also, the higher the frequency, the lower the PSRR will be, but at even higher frequencies the IC will no longer be able to respond and the PSRR will go from a decreasing trend to an increasing trend. Is this true?

Thank you in advance.

  • 0
    TI__Expert 7690 points

    Hello Hirokazu-San,

    The input frequency range you mentioned is above the unity gain frequency of the LDO, where the feedback loop has very little effect. So, the output capacitor dominates along with any parasitics from VIN to VOUT.The gate driver's ability to drive the pass-FET gate at high frequencies also has an effect on PSRR in this region. A larger output capacitor with less equivalent series resistance (ESR) will typically improve PSRR in this region, but it can also actually decrease the PSRR at some frequencies. This is because increasing the output capacitor lowers the unity-gain frequency, causing the open-loop gain to roll off earlier and thus lowering PSRR

    So, depending on the choice of COUT, it is possible that PSRR will fall below 10dB

    Best Regards

    Ishaan