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INA240-Q1: is there a difference at the silicone level between the TSSOP and SOIC packages?

Kenrick Vuong
Prodigy 10 points
Part Number: INA240-Q1
Other Parts Discussed in Thread: INA240

Tool/software:

Hello, we have a customer reporting issues with the output of the INA240 that is relatively odd, and are trying to understand and root-cause the problem. Several questions have come up that we were unable to find the answer to through documentation.

After some operating time (currently ranges from 2-5 hours) one of the three current sense amplifiers in our design starts reporting with a new static offset voltage that is not observed on the ref1/2 pins. This only appears to happen on one of the three devices, and as of right now, never occurs on multiple devices at the same time. The reference voltage being supplied to the IC are the same at all 3 ICs, and during measurement checks we do not observe a difference of this voltage at the 3 devices, so we dont believe it is related to the supply of the reference voltage.

The issue appears to self-resolve with a power cycle of the device, however without a power cycle, the offset remains a consistant value throughout its operation.

This issue only occurs on a design refreash where the INA240 package was changed from the TSSOP package to the SOIC package. No other changes were made to the circuit design for the INA240 portion.

Is there a difference to the silicone within the package, or is the silicone the same in both package types?

Currently in the pcb layout, the shunts being used with the INA240 have raised bodies that are elevated approx 4mm off the board surface. this allowed us to populate the INA240 IC underneath the shunts for the shortest possible distance from the shunt itself. This was the case in both designs. Due to the pinout assignments, this meant that the physical package of the IC was rotated by 90degree when changed from the TSSOP to SOIC. 

Our second question for this matter is, are the IC packages susceptible to potential electromagnetic fields caused by existing below the current sense shunts, and would the orientation of the physical silicone worsen these affects.

Any help would be greatly appreciated in this matter. Thanks.

- Kenrick

  • 0
    TI__Mastermind 34220 points

    Hi Kenrick,

    The silicon is identical for both packages.

    For your second question – we haven’t systematically characterized susceptibility to magnetic field, nor have we heard of past complaint in this nature.

    For the offset, what is the magnitude, and have you observed on an oscilloscope? Make sure it is not oscillating.

    How reliably can the offset be induced? If you swap with another ("good") device on the board, what happens?

    Regards

    Guang

  • 0 in reply to Guang Zhou
    Prodigy 10 points

    Thank Guang for replying so quick.

    For the offset magnitude, it differs between units exhibiting this issue (for context, we have multiple units showing this issue, not just a single unit). They dont all have the same offset between units, however each unit would consistantly have the same offset during the 'failure event'.
    Generally the magnitude of the offset averaged out between all units is around 0.15V offset.
    The offset was not observed with an osciliscope, it was observered through software sampling at 100hz, so any oscillation may be present, but not observed by our measurements.
    My colleagues are saying that they can reliably get the units to fault out once the failure has occured.
    However due to amount of samples, and time since discovery of failure, we have not attempted swap/repair the failed units to determine if that IC is the cause of root cause of the issue. The customer is currently asking us to do 'non-destructive' testing.
    I will update this thread if there is any new information, or if you need any additional info to help us in determining where the issue might be coming from.

    Thanks.

  • 0 in reply to Kenrick Vuong
    TI__Mastermind 34220 points

    Hi Kenrick,

    Thank you for the explanation. I think it will be key to document how to induce the fault, preferably reproduce on bench. This will be very helpful in case of a failure analysis.

    Yes please keep us posted and post back with any update, or via a new thread. We’ll be here to offer any assistance necessary.

    Regards

    Guang