BUF16821 Layout and Design Guidelines

Hello,

 We don’t have a standalone document regarding BUF16821 design and layout, but most information is in the datasheet.  

 A typical application schematic can be seen in the image below.  Here are some basic schematic guidelines:

 1.)  Analog Supply Voltage, Vs
            a.)  +9V - +20VDC required between VS and GNDA
            b.)  Supply decoupling capacitors should be present and located as close as possible to the pins of the IC (Pin 9 and Pin 23).  Use separate decoupling for each VS input pin and do not try to share a single decoupling cap for both inputs.  Use a 10uF and 100nF in parallel for best performance.   

2.)  Digital Supply Voltage, VSD
            a.)  +2V - +5.5V required between VSD and GNDD
            b.)  Supply decoupling capacitors should be present and located as close as possible to the VSD pin of the IC (Pin 13).  Use a 1uF and 100nF in parallel for best performance.

3.)  Digital Communication, I2C
            a.)  Set I2C address using the A0 pin on the BUF16821.
            b.)  I2C is an open-drain communication bus so pull-up resistors are required.  Use values between 4.7k and 47kOhms.  Higher resistance will draw less current but will have slower rise times due to stray capacitance.
            c.)  Avoid parasitic capacitance between SCL and SDA lines by running a GND trace between them.

4.)  Ground, GNDA, GNDD
            a.)  All GND signals must be connected to the same potential.  The connection should not be located far from the BUF16821. 

5.)  Analog Outputs, OUT1 – OUT14, VCOM1, VCOM2.
            a.)  Connect analog outputs to the source-driver inputs.
            b.)  Avoid capacitive loading >1nF on the outputs to avoid issues with overshoot and ringing.
            c.)  Series resistors may be desired for protection.

   The image below is from the datasheet and shows the preferred landing pattern on the PCB for the BUF16821.  Here are the basic layout guidelines:

 1.)  Decoupling Capacitors
           a.)  As mentioned above place the analog and digital supply decoupling capacitors as close to the IC as possible for best effect. 

2.)  I2C Routing
            a.)  To avoid communication issues, stray capacitance should be minimized between SCL and SDA.  This can be accomplished by routing a GND signal between SCL and SDA and trying to prevent the two lines from crossing over each other or running in parallel for long distances.  Never twist SCL and SDA together or route them on a twisted pair cable.  If I2C needs to be run between two boards use two twisted pair wires and twist each line with GND or preferably use a shielded cable with the shield connected to GND.

 3.)  Power Dissipation
           a.)  BUF16821 can drive significant power into loads and to prevent the device junction temperature from exceeding the maximum value of 125C the PowerPAD on the bottom of the BUF16821 must be connected correctly to a copper pour electrically connected to GND.  As shown in the image below an exposed copper pour is located directly under the BUF16821 that will connect to the PowerPAD.  Vias shown in the image connect the PowerPAD to a larger copper pour on an inner or bottom layer that will help move heat out of the BUF16821.  

Best Regards,
Collin Wells
Precision Linear Applications