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TLE2062 Phase Margin Question

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Prodigy 20 points
Other Parts Discussed in Thread: TLE2062

On the TLE2062, it appears the Phase Margin is specified as 58 degrees at unity gain. there is a reference to Figure 3. Figure three has a circuit configuration for a gain of 100, output referred to the input. Please explain this error? If Figure 3 is the configuration for the gain margin what is the real unity gain phase margin?

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    TI__Guru 63600 points

    The open-loop gain/phase is measured using a close-loop inverting configuration and calculated as AOL=20*log (Vout/Vos) so there is no error in the PDS Fig 3.

    The unity gain phase margin is the phase measured at the point where AOL gain crosses 0dB - in the graph below, AOL curves crosses 0dB ~1.3MHz and the corresponding phase margin is 70 degrees (180deg-110deg).  Please see the attached simulation circuit together with post-processed results.

     

    TLE2062 AOL test.TSC