AFE032 DAC mode/Digital filter/

Hello Tarzan,

Below are the answers to your posted questions which are in green text.  If you would like me to review your schematic to double check the hardware side let me know and I can private message you my email to send it. 

Best,

Errol

Hi All,

I intend to implement FCC/CENELENC/ARIB using AFE032 DAC mode,

there are couple questions, please kindly helps,

I following sequence to write samples to the DAC as AFE032 recommend

the parameters as following is current status

for FCC/ARIB sample frequency fs is 1.2MHz, then XCLK is 19.2MHz, SCLK is 19.2MHz, 

1.  set CS is low and Write the first 12-bit word to DIN

2.  Set CS high to indicate that the sample is entered and Wait for at least four SCLK cycles

I am follow Table 10 in AFE032 datasheet. get the DAC_CLK is 4.8MHz and bypass block1,2,and 4, includes Block3 only.

does these configure correct setting?

Yes, this should configure the DAC for a new sample and indicate that the sample is entered after the initial configuration of the following steps.

1. Send a valid XCLK signal to the device.

1. Set CS low.
2. Wait for at least 20 DAC_CLK cycles.
3. Set DAC (pin 7) high. This setting places the device in DAC mode.

1. Write the first 12-bit word to DIN. Note that the DAC register is left-justified.

1. Set CS high to indicate that the sample is entered.

1. Wait for at least four SCLK cycles.

(Q: Shall I set these REG_COEFF1_BLOCK_1/2_MS/LS~REG_COEFF7_BLOCK_1/2_MS/LS when I bypass block1 and 2?)

At first look we concur that you don’t need to set block1 and block 2. We can arrange a schematic review if you would like to make sure hardware that everything is accounted for.

also for CENELENC sample frequency is 400KHz, then XCLK is 19.2MHz, SCLK is 19.2MHz, 

1.  set CS is low and Write the first 12-bit word to DIN

2.  Set CS high to indicate that the sample is entered and Wait for at least 32 SCLK cycles

and Digital filter as like FCC/ARIB 

How was 32 SCLK cycles derived?

the other question, regards to DAC output (pin14)

I have 12bit samples, range [0x800~0x7ff]

I add bias(0x800) on each sample when I send sample through SPI to DAC mode,

I expected DAC out(pin 14) see range [-DAC_NRF~ +DCA_NRF], but Table 4 show it is not.

It cannot have a range from [-DAC_NRF - +DCA_NRF], it can only range from [0 ~ +DAC_NRF]. For example, having a AVDD of 3.3V the ideal DAC range is [0 - 0.7V] with mid-scale at 0.35V. This device is internally design to only this type of range based off AVDD.

the last question is XCLK 19.2M Hz is not 50% duty cycle(High 46.6% and Low is 53.33%)

does it work fine on AFE032?

Typical XCLK should be 50% duty cycle according to datasheet specifications. Whether it is higher or low it should work fine.