Hello team,
How can I think about offset voltage drift in near V+ rail condition?
Datasheet shows offset voltage drift specification with Vcm=(V+)-1.5V as test condition. At same time, OPA2197 Vcm range reaches to V+ rail.
Does offset drift get worse if Vcm is larger than (V+)-1.5V, or remain same?
I think Vcm=(V+)-1.5V condition represents NMOS input operation area, and we can reference the spec for also when Vcm is larger than (V+)-1.5V, correct?
Best regards,