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TLV4111: TLV4111 Spice Model Issue

Peter Ruggiero
Prodigy 70 points
Part Number: TLV4111

Hello,

       I want to build a spice model of a circuit i'm working on but decided to start with a simple model to ensure that the TLV4111 was working correctly.  For some reason the output of the op amp in the configuration below is limiting the output voltage to ~3.5/5 (output voltage/supply voltage).  If i bump the supply voltage up to 8V, the opamp output will then match the opamp input (+).  Any idea why this is happening?

  • 0
    Guru 140200 points

    Hi Peter,

    you are violating the common mode input voltage range and you exceed the maximum supply voltage. Please see the "absolute maximum ratings" and the "recommended operating conditions" on page 3 of datasheet.

    Kai

  • 0 in reply to kai klaas69
    Prodigy 70 points

    Interesting, I didn't see that it wasn't a rail to rail on the input.  When I tested it on the bench I was able to get 4.6V on the output in a unity voltage follow configurationwith a 5v supply up to about 200 mA.  This was with just a resistor load.

    I wonder with the more complicated load in my real circuit if this is why the design is giving me troubles.

    So how do you get rail to rail outputs in a device that doesn't do rail to rail inputs?

  • 0 in reply to Peter Ruggiero
    TI__Guru* 93105 points

    Hi Peter,

    The TLV4111 simulation model is designed such that if the input level exceeds the high end limit of the common-mode voltage (VICR) range (VDD - 1.5 V), the output simply limits at that level. This is to let the user know the VICR limit has been exceeded. The (VDD - 1.5 V) is the minimum that its assured, but in reality the VICR may exceed (VDD - 1.5 V) as you observed with the device you tested on the bench.

    One way that you can configure the TLV4111 such that it can operate with an input range nearly equal to the supplies is to add a voltage divider at the non-inverting input, and then add some gain to the stage to make up for the divider. Below you will see the TLV4111 configured such that the 5 V is divided down to the VICR +3.5 V maximum. The divider has a gain of +0.7 V/V (3.5/5.0). Then, R3 and R4 set the TLV4111 for a non-inverting gain of +1.43 V/V. The overall gain is (0.7 V/V)(1.43 V/V) or 1 V/V.

    The output doesn't swing all the way to the positive supply rail because it is sourcing about 120 ma peak through the output load. There is the normal voltage drop across the output transistor sourcing the current. 

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • 0 in reply to Thomas Kuehl
    Prodigy 70 points

    That makes sense.  I'm curious though what plays into how close the input rail can get to the supply?  I was .4v away and that wasn't because I was trying to get as close to the rail as I could, just happened to be the voltage i needed.  Does the type of load, resistance or capacitance, play into it?

  • 0 in reply to Peter Ruggiero
    TI__Guru* 93105 points

    Hi Peter,

    The design of the input stage and biasing are what establishes the VICR range for an Op amp. All Op amps have a differential amplifier at the front end. In the case of the TLV4111 that differential amplifier consists of a matched CMOS FET pair. However, that is just part of what makes up the Op amp from end. The two FET sources of the differential pair transistors connect to a constant current source. That current divides between them as evenly as possible. On the top end of the input FET drains are load FETs that act as dynamic resistances. 

    At either end of the VICR range the input, current source and load FETS must have a minimum of gate-to-source and source-to-drain bias voltages available to stay within their linear operating ranges. When VICR exceeds the positive swing limit it appears the TLV4111 load FETs run out of linear operating range.

    The output swing of the Op amp is affected by the load placed on its output.

    Regards, Thomas

    Precision Amplifiers Applications Engineering