Hello,
I am try to attenuate a 6V CCD analog output using 2 BUF602 buffers in order to digitize the signal using an AFE. In the first stage, the BUF602 acts as a voltage follower buffer and in the second stage, it is used to buffer the attenuated signal. The signal attenuation is carried out by connecting a series voltage divider at the input of the second stage. I am simulating the circuit in TINA using the equivalent input circuit of the CCD AFE input connected as the load.
After twiddling the power supplies a bit, I found that applying a voltage greater than +7VDC on the +Vs pin avoids signal clipping. When I connect the supply GND to -Vs (i.e. single supply mode), the peak of the signal follows the ccd signal but the minimum signal gets level shifted (and hence the peak to peak voltage of the signal is reduced in the first stage, which is undesired. Moreover, signal distortion is observed in the second stage.
In order to get the buffer to follow the full swing of the input signal, as per simulations carried out in TINA, a small negative voltage (eg. -2V) needs to be applied to the -Vs pin while +7V needs to applied to the +Vs pin. Can the circuit be operated using +7V and -2V (non-symmetrical) power supply?
