Hello,
I'm designing voltage controlled current source using LM2902 as below.
And its loop characteristics is as below.
At around 200kHz, there seems to be complex conjugate pole.
But I can't find what makes complex conjugate pole.
Could you explain about it with equation?
For compensation it, Adding RC circuit and double pole seems to be seperated as below.
Hi David,
The closed-loop ac results you've shared are a result of a circuit stability issue which results in ac gain peaking and rapid phase shifts. For more information on op amp stability please view the TI Precision Labs videos on op amp stability. The small-signal analysis of this circuit is difficult to capture in an equation because of the complexity of the op amp small signal behavior interacting with the NMOS small-signal model. However, we design this circuit often and can help explain why/how to compensate it.
First, op amps often have trouble directly driving a capacitive load. The gate of an NMOS often has a significant capacitance which requires a series resistor between the output of the op amp and gate of the NMOS for the circuit to be stable. However, while required to fix one stability issue, the series R1 resistor interacts with the capacitance forming a delay element in the larger V-I loop which causes a zero in the 1/Beta curve. The open-loop results of the circuit with just the 2k R1 resistor are shown below. Notice that there is a zero in the 1/Beta curve which causes the 1/Beta curve to interact with the Aol curve at a rate of closure of 40dB/decade which is unstable.
In order to compensate the circuit, a 2nd feedback path is required to dominate the circuit feedback at high frequencies. This is accomplished by adding the additional R2 and C1 components. R2 provides a dc feedback path directly at the current setting resistor (R4) and C1provides a high-frequency feedback path that bypasses the NMOS and returns the circuit to a unity-gain buffer at high frequencies. The value or R2 isn't too crucial but the input bias current will flow through it and cause dc errors so it shouldn't be made substantially large. C1 needs to be set such that the high-frequency feedback path is dominant before the zero occurs in the 1/Beta curve. Since the zero occurs around 100kHz the C1 capacitor was set to close the loop directly around the op amp at around 1/3 of this frequency at 33kHz. C1 = 1 / ( 2*pi*R1*33kHz) = 2.4nF so the closest common value of 2.2nF was selected.
Here are the open-loop results of the circuit. Notice that there is a zero in 1/Beta, the rate-of-closure is 40dB/decade and the phase margin is only 4 degrees indicating a very unstable system. With R2 and C1 added the zero is cancelled with the pole from R2/C1 and the phase margin is greater than 50 degrees indicating a stable system.
Here are the transient results of this circuit. Notice the results without R2 and C1 are unstable and have large amounts of overshoot and ringing. The results with R2 and C1 are stable with a nice damped response.
