Hello，
Our customer used INA199 for battery charging measurement , and it worked well during normal operation. But when did the ESD test, it failed at 3KV test, INA199 is very hot. Below circuit is the test environment, now the tested result is 2KV test is passed, but 3KV test failed. Could you please give some suggestions?
Best regards
Kailyn
Hi Kai and Kailyn,
I am going to translate the Chinese on Kailyn's diagram.
Location 1: This connector area is interfacing with outside, also where ESD injections are made during test.
Location 2: D11, D5 and D6 are replaced with 3.3V TVS diode. (see three yellow pointer)
Location 3: Activated outside NMOS (did not say which one, likely Q3), which controls LED status (LED_B?), LED_B point is seen high voltage during failure. (see yellow pointer on the far right).
Location 4: Passed 2kV ESD test, 3kV and greater result heating in U2 (hot to the touch) after test, and is unable to perform self-recovery, failed test.
Questions to Kailyn,
1. Is ESD performance test while EUT is ON or OFF? In other words, Is unit On or Off while the test is being performed?
2. Are there metal casing at JP2 connector?
My speculation:
ESD transient voltage has a path (high impedance path) from ESD injection point (JP2) to U2 (INA199). If JP2 connector and mounting plate are made of metal, they should be grounded. If JP2 and mounting plate are made of plastic (mainly), you need place a metal ground tab or ground shield next or inside of JP2 connector.
When ESD voltage strikes at JP2, high KV has to jump to ground instantly. If you provide a high impedance path to U2, it will damage weakest link along the path. Are there anything got damaged along the path for >3kV? What happened here is that the ESD voltage did not find a ground path near JP2 connector, which the lowest impedance point is likely located near U2.
Best,
Raymond
Hi Raymond, hi Kailyn,
thanks for translating :-)
The layout plays an enormeous role when it comes to ESD. It's extremely important to have a solid ground plane! Can you show the layout?
I would add a BAT54S directly at the output of INA199 and clamp the output voltage to the supply rails. Between the output and D11 I would insert a current limiting resistor. I would even think about adding a cap in parallel to the TVS to slow down the ESD:
Connect this additional cap and the TVS directly at the connector. But connect the current limiting resistor and the BAT54S directly at the INA199. It's also of special importance that the supply decoupling cap of INA199 directly sits at the INA199!
And use the INA199C instead of INA199A. It can withstand a higher ESD voltage.
Kai
