op-amp Cc or Cin

Hello Vish,
I have to see the reference where you have taken your information and your quotes.
I could be wrong, but I think you're dealing with two different device models.

In the case of the miller cap equivalence you've shown, that comes from small signal modelling and equivalent cap value in order to compute bandwidth and roll-off. Miller multiplication is an AC phenomenon.
In the case of computing the device slew rate, you're dealing with large signal behavior where the interstage cap (actual value) is having to be charged and discharged with a fixed amount of current (I_bias). So, I think that's why the miller multiplication does not enter the expression.

Regards,
Hooman

Hello Hooman

Thank u for ur response......i hv not taken from any reference Sir ....i just had the doubt so posted here.
i understand ur points....

one of the member posted this regarding my question in this forum only.

"The Cin equation is good for compensation pole cutoff frequncy 1/(2*Pi*Zout*Cin).
For slew rate, the error amp provides a current to charge a virtually large CIN but small & slow input only applies during the active gain of the transistor and the transistor has gain in proportion to Av therefore Av nearly cancels out. This is why Av is not used in first equation."

So in the above points i did'nt understood this point" the error amp provides a current to charge a virtually large CIN but small & slow input only applies during the active gain of the transistor and the transistor has gain in proportion to Av therefore Av nearly cancels out"

So can u please attached some pdf regarding this or suggest some methods so that i can simulate it and verify it...

regards
vish

Hi Vish,

I'm sorry but I also don't understand the quote you had attached:

" the error amp provides a current to charge a virtually large CIN but small & slow input only applies during the active gain of the transistor and the transistor has gain in proportion to Av therefore Av nearly cancels out".

Here is an EDN article from BruceTrump which may answer your questions:

http://www.edn.com/electronics-blogs/the-signal/4415482/Slew-Rate-the-op-amp-speed-limit

Regards,

Hooman

Hello Hooman

please find the website  reference  below  for which i would  want  to clear  my doubts.

analogictips.com/measuring-opamp-open-loop-gain-spice

i have simulated the op-amp  in the configuration to measure the open loop gain that is given  in the first figure of the above website ...

even i done the simulation on it.....when i performing transient analysis  to calculate open loop gain i observed that  my output dc level is same as the input dc level......So here are my some doubts please clarify on this..

why is the  output following  the input  in the op-amp which is configured to measured the open loop gain using RC negative feedback?

What is the advantage of  this topology ?

regards

vish

Hi Vish,

I've used the 2nd circuit from your link to get the Open Loop Gain / Phase response of the LMH6629, and it looks reasonable to me:

Here is the TINA-TI file associated with the image above:

/cfs-file/__key/communityserver-discussions-components-files/14/3817.LMH6629-Open-Loop-Gain_5F00_Phase-Response-E2E-3_5F00_3_5F00_15.TSC

Your question:

"Why is the  output following  the input  in the op-amp which is configured to measured the open loop gain using RC negative feedback?"

Answer:

The output will follow the input voltage (VG1) according to the Open Loop Gain characteristic of the part. That is 80dB of gain at DC, 55.4dB of gain at 10MHz, and so on. I'm not sure what you mean it "follows the input" since it should not really follow but it would gain-up the input.

One note: When setting up the low pass filter values (R1, and C1), do a DC node voltage analysis first to make sure the value of R1 is not so large that it cannot supply the input bias current that would then create and offset and give you wrong results. In this case, I've chosen the R1 value so that the output is only -148mV DC due to offset created by the input bias current.

Regards,

Hooman

hello Hooman

   Do we really bother about  the phase margin while designing the comparator???

regards

Vish

Hi Vish,

There is no need to be concerned about phase margin because negative feedback is not applied to the comparator input. The comparator operates in a non-linear mode with the output at one supply rail, or the other. Whereas, the operational amplifier operates in linear mode with negative feedback applied. The phase margin concerns apply to that mode of operation.

Regards, Thomas

PA - Linear Applications Engineering

 

Hello Thomas

        What is the relationship between settling time and UGB???

does settling time really affects UGB??

regards

VIsh

Hello Vish,

A relationship between an operational amplifier UGB (GBW, gain-bandwidth) and settling time does exist. I suspect designers do their best to achieve the an acceptable compromise between them i.e. achieveing the widest bandwidth while maintaining reasonable settling times.

Rather than reinventing the wheel, the subject of settling time is effectively covered in the Burr-Brown book, Function Circuits - Design and Applications, by Yu Jen Wong and William Ott. Burr-Brown held the copyrights to the book and those were transferred to TI when Burr-Brown was acquired by TI. Therefore, I have copied the information from the book and attached it in the zip file.

Note that in the discussion the reference to the bandwidth ω_C (2πf_C), which is the closed-loop -3 dB frequency and not the GBW frequency. The closed-loop corner frequency can be related to the GBW using relationships found in TI's new TI Precision Labs series, Bandwidth -2 section:

https://training.ti.com/ti-precision-labs-op-amps-bandwidth-2?cu=14685

Regards, Thomas

PA - Linear Applications Engineering

Set_time&BW.zip

Hi Thomas

what is the maximum gain and ugb can be achieved in single stage differential op-amp and why???

regards

viSh

Hi Vish,

Can you tell us about your application and explain why these parameters are of importance to it? If your questions are accademic that is okay, but we prefer you use the TI Precison Labs resources to obtain information. They provide a wealth of information:

http://www.ti.com/lsds/ti/amplifiers-linear/precision-amplifier-precision-labs.page

Regards, Thomas

PA - Linear Applications Engineering

 

 

Hi THomas

 

it was just my  formal question regardless of any application....are we able to achieve more than 60db and also good UGB in single stage differential 

amplifier only(it is easy to do  single    stage only not going for two stage)...so asked...

regards

Vish

Hello Thomas

AS i asked about Settling time previously...u sended me good pdfs,thanks for that ....what about this .tell me whether this valid or not for the opamp...
AS in case of simple RC filter Ts=5 tou or 7 tou
"usually Ts(Settling time) should be chosen 7 times the RC product(1 tou) So
AS we know f3db=1/2 pi *tou

Ao * F3db = UGB

So tou=Ao/ 2 pi *ugb this is for one tou

similarly we can get for 7 tou...
above this is correct or not??
regards
vish

Hi Vish,

I haven't specifically used that appoximation, but there is one that we do use and is covered in the TI Precision Labs, Slew Rate - 2 session. You can find the derivation on pages 14 and 15:

https://training.ti.com/ti-precision-labs-op-amps-slew-rate-2

or for the sildes:

https://training.ti.com/system/files/docs/1222%20-%20Slew%20Rate%202%20-%20slides_0.pdf

This gets you to the closed-loop, small-signal bandwidth. If that is known, than the UGB can be determined by multiplying the small-signal bandwidth by the closed-loop gain.

Thomas

PA - Linear Applications Engineering