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Stability consideration of voltage buffer

Navroop Singh47
Prodigy 30 points


Hello,

Just a general question regarding stability analysis on voltage follower..

I have seen designs where Voltage (DC Voltage) is buffered by using an OP-Amp which is used as Vref  in the design.

If  loop have 0<PM < 45 , then we will see ringing at the start up and before output signal stabilize to Vref. 

Is this the only time ( at start up ) we will see effect of "not having enough PM" or will there be any other situations where this PM will cause ringing??

Thanks in advance for your comments.

-Navroop-

  • 0
    TI__Mastermind 26908 points

    Even though you only notice the ringing at power up, it is a bad idea to put a circuit into production that has poor phase margin (i.e. less than 45 deg). The reasons are listed below:

    1. 1.      Amplifiers with poor phase margin are sensitive to changes on any pin. Not just the input. So, for example, a reference buffer may have changes on the power supply or load that could cause stability issues. A common case is that the reference buffer is connected to an ADC reference input, and the reference input has loading effects that occur during A/D conversion (i.e. kickback). This “kickback” can cause ringing will can have a significant effect on system accuracy. Remember, the key objective of the reference is to have a very stable and accurate voltage level.
    2. 2.      The factors that determine stability have process variation (e.g. Aol, output impedance). If you measure a phase margin less than 45 deg on one device, than other devices will be different. Some will be more stable and others will be less stable. You may find that you will have marginal stability on devices during initial characterization, but once you go into production some devices oscillate continuously. 

     

    Art