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PGA281 Internal Voltage Range Limits

Other Parts Discussed in Thread: THS4531A

Hello,

I'm trying to make a gain calculator for the PGIA281 so the user can configure the part properly for maximum output signal levels that later feeds a 5V differential input ADC via a THS4531A.  The datasheet specifies the input range as 2.5V in from either rail, but I need to know the levels of the internal saturation points to properly select the gain given that common mode voltages may limit the gains allowed.  Figure 44 shows some key nodes and error detection points in the part.  The maximum voltages allowed at these points are the combined common mode and differential voltages. 

For example, if my rails are +/-15V and the input common mode voltage is (Vcm) 12.4V with a balanced input 200mVpp on each pin or 400mVpp differentially the input level on each pin is +12.5V to +12.3V which meets the input requirements. Now if the outputs of A1 and A2 can swing higher than +12.5V the PGIA GAIN network might be able to be set higher than 1.  If not the PGIA part of the GAIN network is 1 and the secondary gain feeding the DIFF Amp A3 can be scaled for 1.375 with yields a differential output of 550mV PkPk.

In general the common mode voltage will have a gain of 1 at A1/2 output nodes while the differential gain is set by the PGIA part of the GAIN network so if A1/2 clamp symmetrically at +/-Vpgiac I can select the largest binary gain that prevents clipping at the A1/2 outputs.  The outputs of A1 and A2 are balanced so the signal is split equally and the maximum gain allowed is 4 x (Vpgiac - Vcm)/Vdiff where Vdiff is PkPk level between the input pins. 

For the previous example now if the A1/2 outputs clamp at 1.5V inside the rails, Vpgiac is +/-13.5V.  So the maximum gain is 4 x (13.5V - 12.4V)/400mV = 11 and rounding down we get a gain for 8 for the PGIA part of the GAIN network.  Now since the peak value on the input pins is 12.5V with a Vcm of 12.4V a gain of 8 will put the maximum levels at A1/A2 at 12.4V + 0.1V x 8 = 13.2V which is below the 13.5V maximum.  Now the effective differential level going to the DIFF AMP is 3.2V so I can also set the secondary DIFF Amp gain to 1.375 for a final effective differential output of 4.4V PkPk.

Thanks,

Jeff Lee

  • Hello Jeff,

    I believe that you should also consider the maximum linear output voltage of the input amplifiers to be from (VSN + 2.5V) to (VSP - 2.5V). However, I will check with the designer to confirm this.

    Best regards,

    Ian Williams
    Linear Applications Engineer
    Precision Analog - Op Amps

  • Hello Jeff,

    The designer has confirmed that you should remain within 2.5V of VSP and VSN at both the input and output of the input stage amplifiers. Some parts may be able to drive slightly closer to the rails, but for a robust design over process and temperature the 2.5V headroom is recommended.

    I'd be interested to see your calculator once it's complete. Do you plan to release it as free or open-source software?

    Best regards,

    Ian Williams

  • Ian,

    The calculator will be part of our companies Vista software package that is used for telemetry data acquisition setup and processing. The software is not free, but included with the hardware when purchased.

    The main points the software checks are that to properly set up the channel you must provide more than just the pkpk input level, offset and ADC input range. You also need to specify the input common mode voltage, degree of balance between the differential inputs and degree of balance of the offset voltage on the inputs.

    Regards,

    Jeff Lee
  • Jeff,

    Thanks for the clarification. All the best with your hardware/software development!

    Best regards,

    Ian Williams