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DC offset in output of MPY634 used as multiplier

Other Parts Discussed in Thread: MPY634

Hello,

I am using the TI MPY634 in a standard multiplier/squarer configuration. I have included photos of my schematic and breadboard:

At low frequencies (<100 kHz), it behaves as expected. However, at higher frequencies, there is a significant growth of a DC offset in the output.

Here are some sample shots of the reading I am getting on the scope for demonstration:

Channel 1 is the output of the multiplier/squarer, channel 3 is the input straight from the function generator for reference.

Driven at 100 kHz (Normal)

Driven at 1 MHz (small DC offset)

Driven at 2 MHz (larger DC offset, notice the increase in Ch1 mean, the signal is barely visible at the top of the screen)

In general the DC offset seems to grow with frequency above 100 kHz.

Is there something that I am missing? from what I understand this multiplier should operate well at these frequencies as it has 10 MHz bandwidth and I am not using a feedback attenuator. The DC offset is greater than the specification says the input offset voltage should max out at 100 mV when being used at 2 MHz so I do not think that this is the cause. Also, my application is not well suited for trimming as I need to read out the proper DC level of the multiplied signal at various frequencies.

  • Hi Alex,

    We don't have any information about the MPY634 squarer function beyond what is provided in the datasheet. We have to rely on it and general knowledge about Gilbert cell multipliers for a possible answer. 

    It appears that the squarer circuit produces not only an ac waveform having 2x the input frequency, but also a dc term. That dc term is present in the following derivation:

    The first term in the last equation represents a dc level. However, further analysis shows that the dc level is independent of the frequency. Thus, one would expect the dc level to remain constant if the multiplier were ideal and didn't exhibit any changes with frequency.

    The datasheet doesn't provides any direct clues why the output dc offset changes with frequency. My thought is the X and Y input amplifiers although similar are not exactly identical in design and layout. They match well at dc where most of the electrical specifications are set, but begin to exhibit differences in electrical performances as the frequency is increased. The offset shift is an outcome.

    Some hints that they are different are the Non-linearity and Feed-through specifications in the Electrical Characteristics table, and the Feed-through vs. Frequency graph on datasheet Pg. 4. It is difficult to determine what exactly is changing internal to the MPY634, to such a level, as to cause the large output offset changes with frequency. 

    The datasheet mentions on Pg. 8 for the frequency doubler that "The DC output component is removed by AC-coupling the output." If your application doesn't need to operate down to dc, then ac output coupling may be a solution. 

    If the circuit must operate at dc, then a different solution should be pursued.

    Regards, Thomas

    PA - Linear Applications Engineering

  • Hi Alex
    Have you resolved the problem?
    I faced with the same issue
    e2e.ti.com/.../577115
    Best
    Oleg