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Linux/DRA750: Audio interface without codec support

Part Number: DRA750

Tool/software: Linux

Hi all,

1. I have a issue with audio play and record (without codec support).

2. Test mechanism as follow:

      2.1 Adapt Board with GLSDK 3.00.00.03, mcasp3 be master with i2s mode.

      2.2 Carrier Board with GLSDK 7.02.00.02 mcasp3 be slave with i2s mode.

      2.3 Adapt Board connect with Carrier board

      2.4 I want to use alsa tools (aplay and arecord) to do 1k tone wav file play and record. Both Carrier board and Adapt board will play and record 1k tone file.

3. Attach our schematic:

Schematic.docx

4. Does ASoC support this test mechanism WITHOUT codec support?

Thank you very much.

BRs

Andy

  • Hi Andy,

    I have forwarded your question to an audio expert.

    Regards,
    Yordan
  • Hi Andy,

    It's possible to have a CPU DAI (McASP) connected to a dummy codec (i.e. sound/soc/codecs/bt-sco.c). What is the sampling rate of the audio data transferred in that McASP-to-McASP link?

    The BT SCO codec driver supports 8 and 16 kHz, for those two rates you just need to enable and glue that driver to McASP3 on each kernel/board (i.e. via dts).

    If higher sampling rates are needed, you may need to create your own dummy codec driver and specify the SNDRV_PCM_RATE_* that are needed in your system.

    Then, you should be able to do aplay on one board and arecord on the other board.

  • Hi Yordan,

    1. I change codec from tlv320aic3x to bt-sco on GLSDK 7.02.00.02 (Carrier Board) and 3.00.00.03 (Adapt Board).

    2. Both has different issues:

          2.1 In Adapt Board (3.00.00.03):
                It seems a impact to minimum channel support to bt-sco and davinci-mcasp.
                Davinci-mcasp in i2s mode, playback, minimum channel is 2 but bt-sco playback minimum channel is 1.
                It will cause match error when aplay api play wav file.

          2.2 In Carrier Board (7.02.00.02): 
                I use ALSA API to play wav file, and the log as below

    ======================================= LOG ================================================
    root@wnc-cb:~# aplay -D hw:0 1kHz_48000Hz_16bit_120sec.wav
    Playing WAVE '1kHz_48000Hz_16bit_120sec.wav' : Signed 16 bit Little Endian, Rate 48000 Hz, Mono
    aplay: set_params:1204: Broken configuration for this PCM: no configurations available
    root@wnc-cb:~#
    ===========================================================================================

    Could you please help these issue. To 2.1, Can I just decrease davinci-mcasp i2s mode (playback) minimum channel to 1?

    BRs
    Louis

  • Louis,

    McASP supports mono audio only in a 2-TDM slot fashion. That is, one slot (the first one) carries the audio data, and the other slot is zero-padded. McASP doesn't support mono in a single TDM slot.

    Please take a look at this patch which adds support for mono:
    git.omapzoom.com/

    Since you mentioned that the audio link between the two McASP instances is I2S, that's technically a stereo link. I mentioned the bt-sco as an example of a dummy codec. If the bt-sco doesn't meet your sample rate or channel reqs, then you may need to create your own dummy driver.

    Also, the hw_params in your logs seem to indicate that this link is not precisely for SCO but to for A2DP. Please confirm. If so, the bt-sco is not the right codec for your usecase.
  • Hi Misael,

    The following is my response, please help, thank you.

    -

    -

    -

    McASP supports mono audio only in a 2-TDM slot fashion. That is, one slot (the first one) carries the audio data, and the other slot is zero-padded. McASP doesn't support mono in a single TDM slot.

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

    [Louis] --> the following is my DTS configuration, tdm-slots is 2, op-mode is in I2S

    1511 &mcasp3 {

    1512         #sound-dai-cells = <0>;

    1513         fck_parent = "atl_clkin2_ck";

    1514

    1515         pinctrl-names = "default";

    1516         pinctrl-0 = <&mcasp3_pins>;

    1517

    1518         status = "okay";

    1519

    1520         op-mode = <0>;          /* MCASP_IIS_MODE */

    1521         tdm-slots = <2>;

    1522         /* 4 serializer */

    1523         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */

    1524                 2 1 0 0

    1525         >;

    1526         tx-num-evt = <8>;

    1527         rx-num-evt = <8>;

    1528 };

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

    -

    -

    -

    Please take a look at this patch which adds support for mono:

    git.omapzoom.com/

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

    [Louis] GLSDK in Carrier Board is 7.02.00.02, the following shows I patch

    diff --git a/board-support/R01_linux-wnc-cb/sound/soc/davinci/davinci-mcasp.c b/board-support/R01_linux-wnc-cb/sound/soc/davinci/davinci-mcasp.c

    index 4157273..637655e 100644

    --- a/board-support/R01_linux-wnc-cb/sound/soc/davinci/davinci-mcasp.c

    +++ b/board-support/R01_linux-wnc-cb/sound/soc/davinci/davinci-mcasp.c

    @@ -1098,7 +1098,11 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,

           snd_pcm_hw_constraint_minmax(substream->runtime,

                                        SNDRV_PCM_HW_PARAM_CHANNELS,

    +#if 0

                                        1, max_channels);

    +#else

    +                                    0, max_channels);

    +#endif

    [Louis] I also append mcasp driver that I used...

    3480.davinci-mcasp.c
    /*
     * ALSA SoC McASP Audio Layer for TI DAVINCI processor
     *
     * Multi-channel Audio Serial Port Driver
     *
     * Author: Nirmal Pandey <n-pandey@ti.com>,
     *         Suresh Rajashekara <suresh.r@ti.com>
     *         Steve Chen <schen@.mvista.com>
     *
     * Copyright:   (C) 2009 MontaVista Software, Inc., <source@mvista.com>
     * Copyright:   (C) 2009  Texas Instruments, India
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    
    #include <linux/init.h>
    #include <linux/module.h>
    #include <linux/device.h>
    #include <linux/slab.h>
    #include <linux/delay.h>
    #include <linux/io.h>
    #include <linux/clk.h>
    #include <linux/pm_runtime.h>
    #include <linux/of.h>
    #include <linux/of_platform.h>
    #include <linux/of_device.h>
    #include <linux/math64.h>
    
    #include <sound/asoundef.h>
    #include <sound/core.h>
    #include <sound/pcm.h>
    #include <sound/pcm_params.h>
    #include <sound/initval.h>
    #include <sound/soc.h>
    #include <sound/dmaengine_pcm.h>
    #include <sound/omap-pcm.h>
    
    #include "davinci-pcm.h"
    #include "edma-pcm.h"
    #include "davinci-mcasp.h"
    
    #define MCASP_MAX_AFIFO_DEPTH	64
    
    struct davinci_mcasp_context {
    	u32	txfmtctl;
    	u32	rxfmtctl;
    	u32	txfmt;
    	u32	rxfmt;
    	u32	aclkxctl;
    	u32	aclkrctl;
    	u32	ahclkxctl;
    	u32	ahclkrctl;
    	u32	pdir;
    	u32	rxmask;
    	u32	txmask;
    	u32	rxtdm;
    	u32	txtdm;
    	u32	rfifoctl;
    	u32	wfifoctl;
    	u32	*xrsrctl;
    
    	bool	pm_state;
    };
    
    struct davinci_mcasp_ruledata {
    	struct davinci_mcasp *mcasp;
    	int serializers;
    };
    
    struct davinci_mcasp {
    	struct davinci_pcm_dma_params dma_params[2];
    	struct snd_dmaengine_dai_dma_data dma_data[2];
    	void __iomem *base;
    	u32 fifo_base;
    	struct device *dev;
    	struct snd_pcm_substream *substreams[2];
    	unsigned int dai_fmt;
    
    	/* McASP specific data */
    	int	tdm_slots;
    	u8	op_mode;
    	u8	num_serializer;
    	u8	*serial_dir;
    	u8	version;
    	u8	bclk_div;
    	u16	bclk_lrclk_ratio;
    	int	streams;
    	u32	revision;
    
    	int	sysclk_freq;
    	bool	bclk_master;
    
    	/* McASP FIFO related */
    	u8	txnumevt;
    	u8	rxnumevt;
    
    	bool	dat_port;
    
    	/* Used for comstraint setting on the second stream */
    	u32	channels;
    
    #ifdef CONFIG_PM_SLEEP
    	struct davinci_mcasp_context context;
    #endif
    
    	struct davinci_mcasp_ruledata ruledata[2];
    	struct snd_pcm_hw_constraint_list chconstr[2];
    #if IS_ENABLED(CONFIG_DISPLAY_DRA7EVM_ENCODER_TPD12S015)
    	bool	is_mcasp8;
    	u8	hdmi_sel_gpio;
    #endif
    };
    
    static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
    				  u32 val)
    {
    	void __iomem *reg = mcasp->base + offset;
    	__raw_writel(__raw_readl(reg) | val, reg);
    }
    
    static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
    				  u32 val)
    {
    	void __iomem *reg = mcasp->base + offset;
    	__raw_writel((__raw_readl(reg) & ~(val)), reg);
    }
    
    static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
    				  u32 val, u32 mask)
    {
    	void __iomem *reg = mcasp->base + offset;
    	__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
    }
    
    static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
    				 u32 val)
    {
    	__raw_writel(val, mcasp->base + offset);
    }
    
    static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
    {
    	return (u32)__raw_readl(mcasp->base + offset);
    }
    
    static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
    {
    	int i = 0;
    
    	mcasp_set_bits(mcasp, ctl_reg, val);
    
    	/* programming GBLCTL needs to read back from GBLCTL and verfiy */
    	/* loop count is to avoid the lock-up */
    	for (i = 0; i < 1000; i++) {
    		if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
    			break;
    	}
    
    	if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
    		printk(KERN_ERR "GBLCTL write error\n");
    }
    
    static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
    {
    	u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
    	u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
    
    	return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
    }
    
    static void mcasp_start_rx(struct davinci_mcasp *mcasp)
    {
    	if (mcasp->rxnumevt) {	/* enable FIFO */
    		u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
    
    		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
    		mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
    	}
    
    	/* Start clocks */
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
    	/*
    	 * When ASYNC == 0 the transmit and receive sections operate
    	 * synchronously from the transmit clock and frame sync. We need to make
    	 * sure that the TX signlas are enabled when starting reception.
    	 */
    	if (mcasp_is_synchronous(mcasp)) {
    		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
    		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
    	}
    
    	/* Activate serializer(s) */
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
    	/* Release RX state machine */
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
    	/* Release Frame Sync generator */
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
    	if (mcasp_is_synchronous(mcasp))
    		mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
    
    	/* enable rececive overrun IRQ */
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, ROVRN);
    }
    
    static void mcasp_start_tx(struct davinci_mcasp *mcasp)
    {
    	u32 cnt;
    
    	if (mcasp->txnumevt) {	/* enable FIFO */
    		u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
    
    		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
    		mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
    	}
    
    	/* Start clocks */
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
    	/* Activate serializer(s) */
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
    
    	/* wait for XDATA to be cleared */
    	cnt = 0;
    	while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) &
    		 ~XRDATA) && (cnt < 100000))
    		cnt++;
    
    	/* Release TX state machine */
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
    	/* Release Frame Sync generator */
    	mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
    
    	/* enable transmit underrun IRQ */
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, XUNDRN);
    }
    
    static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
    {
    	mcasp->streams++;
    
    	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
    		mcasp_start_tx(mcasp);
    	else
    		mcasp_start_rx(mcasp);
    }
    
    static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
    {
    	/* disable IRQ sources */
    	mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, ROVRN);
    
    	/*
    	 * In synchronous mode stop the TX clocks if no other stream is
    	 * running
    	 */
    	if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
    		mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
    
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
    
    	if (mcasp->rxnumevt) {	/* disable FIFO */
    		u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
    
    		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
    	}
    }
    
    static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
    {
    	u32 val = 0;
    
    	/* disable IRQ sources */
    	mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, XUNDRN);
    
    	/*
    	 * In synchronous mode keep TX clocks running if the capture stream is
    	 * still running.
    	 */
    	if (mcasp_is_synchronous(mcasp) && mcasp->streams)
    		val =  TXHCLKRST | TXCLKRST | TXFSRST;
    
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
    
    	if (mcasp->txnumevt) {	/* disable FIFO */
    		u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
    
    		mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
    	}
    }
    
    static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
    {
    	mcasp->streams--;
    
    	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
    		mcasp_stop_tx(mcasp);
    	else
    		mcasp_stop_rx(mcasp);
    }
    
    static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
    {
    	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
    	struct snd_pcm_substream *substream;
    	u32 stat;
    
    	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
    	if (stat & XUNDRN) {
    		dev_warn(mcasp->dev, "Transmit buffer underflow\n");
    		substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
    		if (substream) {
    			snd_pcm_stream_lock_irq(substream);
    			if (snd_pcm_running(substream))
    				snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
    			snd_pcm_stream_unlock_irq(substream);
    		}
    	}
    
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, stat);
    
    	return IRQ_HANDLED;
    }
    
    static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
    {
    	struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
    	struct snd_pcm_substream *substream;
    	u32 stat;
    
    	stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
    	if (stat & ROVRN) {
    		dev_warn(mcasp->dev, "Receive buffer overflow\n");
    		substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
    		if (substream) {
    			snd_pcm_stream_lock_irq(substream);
    			if (snd_pcm_running(substream))
    				snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
    			snd_pcm_stream_unlock_irq(substream);
    		}
    	}
    
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, stat);
    
    	return IRQ_HANDLED;
    }
    
    static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
    					 unsigned int fmt)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
    	int ret = 0;
    	u32 data_delay;
    	bool fs_pol_rising;
    	bool inv_fs = false;
    
    	if (!fmt)
    		return 0;
    
    	pm_runtime_get_sync(mcasp->dev);
    	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
    	case SND_SOC_DAIFMT_DSP_A:
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
    		/* 1st data bit occur one ACLK cycle after the frame sync */
    		data_delay = 1;
    		break;
    	case SND_SOC_DAIFMT_DSP_B:
    	case SND_SOC_DAIFMT_AC97:
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
    		/* No delay after FS */
    		data_delay = 0;
    		break;
    	case SND_SOC_DAIFMT_I2S:
    		/* configure a full-word SYNC pulse (LRCLK) */
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
    		/* 1st data bit occur one ACLK cycle after the frame sync */
    		data_delay = 1;
    		/* FS need to be inverted */
    		inv_fs = true;
    		break;
    	case SND_SOC_DAIFMT_LEFT_J:
    		/* configure a full-word SYNC pulse (LRCLK) */
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
    		/* No delay after FS */
    		data_delay = 0;
    		break;
    	default:
    		ret = -EINVAL;
    		goto out;
    	}
    
    	mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
    		       FSXDLY(3));
    	mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
    		       FSRDLY(3));
    
    	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
    	case SND_SOC_DAIFMT_CBS_CFS:
    		/* codec is clock and frame slave */
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
    
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
    
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
    		mcasp->bclk_master = 1;
    		break;
    	case SND_SOC_DAIFMT_CBM_CFS:
    		/* codec is clock master and frame slave */
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
    
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
    
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
    		mcasp->bclk_master = 0;
    		break;
    	case SND_SOC_DAIFMT_CBM_CFM:
    		/* codec is clock and frame master */
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
    
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
    
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
    			       ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
    		mcasp->bclk_master = 0;
    		break;
    	default:
    		ret = -EINVAL;
    		goto out;
    	}
    
    	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
    	case SND_SOC_DAIFMT_IB_NF:
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
    		fs_pol_rising = true;
    		break;
    	case SND_SOC_DAIFMT_NB_IF:
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
    		fs_pol_rising = false;
    		break;
    	case SND_SOC_DAIFMT_IB_IF:
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
    		fs_pol_rising = false;
    		break;
    	case SND_SOC_DAIFMT_NB_NF:
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
    		fs_pol_rising = true;
    		break;
    	default:
    		ret = -EINVAL;
    		goto out;
    	}
    
    	if (inv_fs)
    		fs_pol_rising = !fs_pol_rising;
    
    	if (fs_pol_rising) {
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
    	} else {
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
    	}
    
    	mcasp->dai_fmt = fmt;
    out:
    	pm_runtime_put(mcasp->dev);
    	return ret;
    }
    
    static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
    				      int div, bool explicit)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
    
    	pm_runtime_get_sync(mcasp->dev);
    	switch (div_id) {
    	case 0:		/* MCLK divider */
    		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
    			       AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
    		mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
    			       AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
    		break;
    
    	case 1:		/* BCLK divider */
    		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
    			       ACLKXDIV(div - 1), ACLKXDIV_MASK);
    		mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
    			       ACLKRDIV(div - 1), ACLKRDIV_MASK);
    		if (explicit)
    			mcasp->bclk_div = div;
    		break;
    
    	case 2:		/* BCLK/LRCLK ratio */
    		mcasp->bclk_lrclk_ratio = div;
    		break;
    
    	default:
    		return -EINVAL;
    	}
    
    	pm_runtime_put(mcasp->dev);
    	return 0;
    }
    
    static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
    				    int div)
    {
    	return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1);
    }
    
    static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
    				    unsigned int freq, int dir)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
    
    	pm_runtime_get_sync(mcasp->dev);
    	if (dir == SND_SOC_CLOCK_OUT) {
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
    	} else {
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
    	}
    
    	mcasp->sysclk_freq = freq;
    
    	pm_runtime_put(mcasp->dev);
    	return 0;
    }
    
    static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
    				       int word_length)
    {
    	u32 fmt;
    	u32 tx_rotate = (word_length / 4) & 0x7;
    	u32 mask = (1ULL << word_length) - 1;
    	/*
    	 * For captured data we should not rotate, inversion and masking is
    	 * enoguh to get the data to the right position:
    	 * Format	  data from bus		after reverse (XRBUF)
    	 * S16_LE:	|LSB|MSB|xxx|xxx|	|xxx|xxx|MSB|LSB|
    	 * S24_3LE:	|LSB|DAT|MSB|xxx|	|xxx|MSB|DAT|LSB|
    	 * S24_LE:	|LSB|DAT|MSB|xxx|	|xxx|MSB|DAT|LSB|
    	 * S32_LE:	|LSB|DAT|DAT|MSB|	|MSB|DAT|DAT|LSB|
    	 */
    	u32 rx_rotate = 0;
    
    	/*
    	 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
    	 * callback, take it into account here. That allows us to for example
    	 * send 32 bits per channel to the codec, while only 16 of them carry
    	 * audio payload.
    	 * The clock ratio is given for a full period of data (for I2S format
    	 * both left and right channels), so it has to be divided by number of
    	 * tdm-slots (for I2S - divided by 2).
    	 */
    	if (mcasp->bclk_lrclk_ratio) {
    		u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
    
    		/*
    		 * When we have more bclk then it is needed for the data, we
    		 * need to use the rotation to move the received samples to have
    		 * correct alignment.
    		 */
    		rx_rotate = (slot_length - word_length) / 4;
    		word_length = slot_length;
    	}
    
    	/* mapping of the XSSZ bit-field as described in the datasheet */
    	fmt = (word_length >> 1) - 1;
    
    	if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
    		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
    			       RXSSZ(0x0F));
    		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
    			       TXSSZ(0x0F));
    		mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
    			       TXROT(7));
    		mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
    			       RXROT(7));
    		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
    	}
    
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
    
    	return 0;
    }
    
    static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
    				 int period_words, int channels)
    {
    	struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
    	struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
    	int i;
    	u8 tx_ser = 0;
    	u8 rx_ser = 0;
    	u8 slots = mcasp->tdm_slots;
    	u8 max_active_serializers = (channels + slots - 1) / slots;
    	int active_serializers, numevt, n;
    	u32 reg;
    	/* Default configuration */
    	if (mcasp->version < MCASP_VERSION_3)
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
    
    	/* All PINS as McASP */
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
    
    	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
    		mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
    	} else {
    		mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
    	}
    
    	for (i = 0; i < mcasp->num_serializer; i++) {
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
    			       mcasp->serial_dir[i]);
    		if (mcasp->serial_dir[i] == TX_MODE &&
    					tx_ser < max_active_serializers) {
    			mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
    			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
    				       DISMOD_LOW, DISMOD_MASK);
    			tx_ser++;
    		} else if (mcasp->serial_dir[i] == RX_MODE &&
    					rx_ser < max_active_serializers) {
    			mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
    			rx_ser++;
    		} else {
    			mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
    				       SRMOD_INACTIVE, SRMOD_MASK);
    		}
    	}
    
    	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
    		active_serializers = tx_ser;
    		numevt = mcasp->txnumevt;
    		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
    	} else {
    		active_serializers = rx_ser;
    		numevt = mcasp->rxnumevt;
    		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
    	}
    
    	if (active_serializers < max_active_serializers) {
    		dev_warn(mcasp->dev, "stream has more channels (%d) than are "
    			 "enabled in mcasp (%d)\n", channels,
    			 active_serializers * slots);
    		return -EINVAL;
    	}
    
    	/* AFIFO is not in use */
    	if (!numevt) {
    		/* Configure the burst size for platform drivers */
    		if (active_serializers > 1) {
    			/*
    			 * If more than one serializers are in use we have one
    			 * DMA request to provide data for all serializers.
    			 * For example if three serializers are enabled the DMA
    			 * need to transfer three words per DMA request.
    			 */
    			dma_params->fifo_level = active_serializers;
    			dma_data->maxburst = active_serializers;
    		} else {
    			dma_params->fifo_level = 0;
    			dma_data->maxburst = 0;
    		}
    		return 0;
    	}
    
    	if (period_words % active_serializers) {
    		dev_err(mcasp->dev, "Invalid combination of period words and "
    			"active serializers: %d, %d\n", period_words,
    			active_serializers);
    		return -EINVAL;
    	}
    
    	/*
    	 * Calculate the optimal AFIFO depth for platform side:
    	 * The number of words for numevt need to be in steps of active
    	 * serializers.
    	 */
    	n = numevt % active_serializers;
    	if (n)
    		numevt += (active_serializers - n);
    	while (period_words % numevt && numevt > 0)
    		numevt -= active_serializers;
    	if (numevt <= 0)
    		numevt = active_serializers;
    
    	mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
    	mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
    
    	/* Configure the burst size for platform drivers */
    	if (numevt == 1)
    		numevt = 0;
    	dma_params->fifo_level = numevt;
    	dma_data->maxburst = numevt;
    
    	return 0;
    }
    
    static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
    			      int channels)
    {
    	int i, active_slots;
    	int total_slots;
    	int active_serializers;
    	u32 mask = 0;
    	u32 busel = 0;
    
    	total_slots = mcasp->tdm_slots;
    
    	/*
    	 * If more than one serializer is needed, then use them with
    	 * their specified tdm_slots count. Otherwise, one serializer
    	 * can cope with the transaction using as many slots as channels
    	 * in the stream, requires channels symmetry
    	 */
    	active_serializers = (channels + total_slots - 1) / total_slots;
    	if (active_serializers == 1)
    		active_slots = channels;
    	else
    		active_slots = total_slots;
    
    	for (i = 0; i < active_slots; i++)
    		mask |= (1 << i);
    
    	mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
    
    	if (!mcasp->dat_port)
    		busel = TXSEL;
    
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
    	mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
    		       FSXMOD(total_slots), FSXMOD(0x1FF));
    
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
    	mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
    		       FSRMOD(total_slots), FSRMOD(0x1FF));
    
    	return 0;
    }
    
    /* S/PDIF */
    static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
    			      unsigned int rate)
    {
    	u32 cs_value = 0;
    	u8 *cs_bytes = (u8*) &cs_value;
    
    	/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
    	   and LSB first */
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
    
    	/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
    
    	/* Set the TX tdm : for all the slots */
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
    
    	/* Set the TX clock controls : div = 1 and internal */
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
    
    	mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
    
    	/* Only 44100 and 48000 are valid, both have the same setting */
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
    
    	/* Enable the DIT */
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
    
    	/* Set S/PDIF channel status bits */
    	cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
    	cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
    
    	switch (rate) {
    	case 22050:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
    		break;
    	case 24000:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
    		break;
    	case 32000:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
    		break;
    	case 44100:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
    		break;
    	case 48000:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
    		break;
    	case 88200:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
    		break;
    	case 96000:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
    		break;
    	case 176400:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
    		break;
    	case 192000:
    		cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
    		break;
    	default:
    		printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
    		return -EINVAL;
    	}
    
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
    
    	return 0;
    }
    
    static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
    				      unsigned int bclk_freq,
    				      int *error_ppm)
    {
    	int div = mcasp->sysclk_freq / bclk_freq;
    	int rem = mcasp->sysclk_freq % bclk_freq;
    
    	if (rem != 0) {
    		if (div == 0 ||
    		    ((mcasp->sysclk_freq / div) - bclk_freq) >
    		    (bclk_freq - (mcasp->sysclk_freq / (div+1)))) {
    			div++;
    			rem = rem - bclk_freq;
    		}
    	}
    	if (error_ppm)
    		*error_ppm =
    			(div*1000000 + (int)div64_long(1000000LL*rem,
    						       (int)bclk_freq))
    			/div - 1000000;
    
    	return div;
    }
    
    static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
    					struct snd_pcm_hw_params *params,
    					struct snd_soc_dai *cpu_dai)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
    	struct davinci_pcm_dma_params *dma_params =
    					&mcasp->dma_params[substream->stream];
    	int word_length;
    	int channels = params_channels(params);
    	int period_size = params_period_size(params);
    	int ret;
    
    	/*
    	 * If mcasp is BCLK master, and a BCLK divider was not provided by
    	 * the machine driver, we need to calculate the ratio.
    	 */
    	if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
    		int slots = mcasp->tdm_slots;
    		int rate = params_rate(params);
    		int sbits = params_width(params);
    		int ppm, div;
    
    		div = davinci_mcasp_calc_clk_div(mcasp, rate*sbits*slots,
    						 &ppm);
    		if (ppm)
    			dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
    				 ppm);
    
    		__davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0);
    	}
    
    	ret = mcasp_common_hw_param(mcasp, substream->stream,
    				    period_size * channels, channels);
    	if (ret)
    		return ret;
    
    	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
    		ret = mcasp_dit_hw_param(mcasp, params_rate(params));
    	else
    		ret = mcasp_i2s_hw_param(mcasp, substream->stream,
    					 channels);
    
    	if (ret)
    		return ret;
    
    	switch (params_format(params)) {
    	case SNDRV_PCM_FORMAT_U8:
    	case SNDRV_PCM_FORMAT_S8:
    		dma_params->data_type = 1;
    		word_length = 8;
    		break;
    
    	case SNDRV_PCM_FORMAT_U16_LE:
    	case SNDRV_PCM_FORMAT_S16_LE:
    		dma_params->data_type = 2;
    		word_length = 16;
    		break;
    
    	case SNDRV_PCM_FORMAT_U24_3LE:
    	case SNDRV_PCM_FORMAT_S24_3LE:
    		dma_params->data_type = 3;
    		word_length = 24;
    		break;
    
    	case SNDRV_PCM_FORMAT_U24_LE:
    	case SNDRV_PCM_FORMAT_S24_LE:
    		dma_params->data_type = 4;
    		word_length = 24;
    		break;
    
    	case SNDRV_PCM_FORMAT_U32_LE:
    	case SNDRV_PCM_FORMAT_S32_LE:
    		dma_params->data_type = 4;
    		word_length = 32;
    		break;
    
    	default:
    		printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
    		return -EINVAL;
    	}
    
    	if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
    		dma_params->acnt = 4;
    	else
    		dma_params->acnt = dma_params->data_type;
    
    	davinci_config_channel_size(mcasp, word_length);
    
    	if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE)
    		mcasp->channels = channels;
    
    	return davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
    }
    
    static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
    				     int cmd, struct snd_soc_dai *cpu_dai)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
    	int ret = 0;
    
    	switch (cmd) {
    	case SNDRV_PCM_TRIGGER_RESUME:
    	case SNDRV_PCM_TRIGGER_START:
    	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
    		davinci_mcasp_start(mcasp, substream->stream);
    		break;
    	case SNDRV_PCM_TRIGGER_SUSPEND:
    	case SNDRV_PCM_TRIGGER_STOP:
    	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
    		davinci_mcasp_stop(mcasp, substream->stream);
    		break;
    
    	default:
    		ret = -EINVAL;
    	}
    
    	return ret;
    }
    
    static const unsigned int davinci_mcasp_dai_rates[] = {
    	8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
    	88200, 96000, 176400, 192000,
    };
    
    #define DAVINCI_MAX_RATE_ERROR_PPM 1000
    
    static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
    				      struct snd_pcm_hw_rule *rule)
    {
    	struct davinci_mcasp_ruledata *rd = rule->private;
    	struct snd_interval *ri =
    		hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
    	int sbits = params_width(params);
    	int slots = rd->mcasp->tdm_slots;
    	struct snd_interval range;
    	int i;
    
    	snd_interval_any(&range);
    	range.empty = 1;
    
    	for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
    		if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
    			uint bclk_freq = sbits*slots*
    				davinci_mcasp_dai_rates[i];
    			int ppm;
    
    			davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
    			if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
    				if (range.empty) {
    					range.min = davinci_mcasp_dai_rates[i];
    					range.empty = 0;
    				}
    				range.max = davinci_mcasp_dai_rates[i];
    			}
    		}
    	}
    
    	dev_dbg(rd->mcasp->dev,
    		"Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
    		ri->min, ri->max, range.min, range.max, sbits, slots);
    
    	return snd_interval_refine(hw_param_interval(params, rule->var),
    				   &range);
    }
    
    static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
    					struct snd_pcm_hw_rule *rule)
    {
    	struct davinci_mcasp_ruledata *rd = rule->private;
    	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
    	struct snd_mask nfmt;
    	int rate = params_rate(params);
    	int slots = rd->mcasp->tdm_slots;
    	int i, count = 0;
    
    	snd_mask_none(&nfmt);
    
    	for (i = 0; i < SNDRV_PCM_FORMAT_LAST; i++) {
    		if (snd_mask_test(fmt, i)) {
    			uint bclk_freq = snd_pcm_format_width(i)*slots*rate;
    			int ppm;
    
    			davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, &ppm);
    			if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
    				snd_mask_set(&nfmt, i);
    				count++;
    			}
    		}
    	}
    	dev_dbg(rd->mcasp->dev,
    		"%d possible sample format for %d Hz and %d tdm slots\n",
    		count, rate, slots);
    
    	return snd_mask_refine(fmt, &nfmt);
    }
    
    static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
    				 struct snd_soc_dai *cpu_dai)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
    	struct davinci_mcasp_ruledata *ruledata =
    					&mcasp->ruledata[substream->stream];
    	u32 max_channels = 0;
    	int i, dir;
    
    	mcasp->substreams[substream->stream] = substream;
    
    	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
    		return 0;
    
    	/*
    	 * Limit the maximum allowed channels for the first stream:
    	 * number of serializers for the direction * tdm slots per serializer
    	 */
    	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
    		dir = TX_MODE;
    	else
    		dir = RX_MODE;
    
    	for (i = 0; i < mcasp->num_serializer; i++) {
    		if (mcasp->serial_dir[i] == dir)
    			max_channels++;
    	}
    	ruledata->serializers = max_channels;
    	max_channels *= mcasp->tdm_slots;
    	/*
    	 * If the already active stream has less channels than the calculated
    	 * limnit based on the seirializers * tdm_slots, we need to use that as
    	 * a constraint for the second stream.
    	 * Otherwise (first stream or less allowed channels) we use the
    	 * calculated constraint.
    	 */
    	if (mcasp->channels && mcasp->channels < max_channels)
    		max_channels = mcasp->channels;
    
    	snd_pcm_hw_constraint_minmax(substream->runtime,
    				     SNDRV_PCM_HW_PARAM_CHANNELS,
    #if 0
    				     1, max_channels);
    #else
    				     0, max_channels);
    #endif
    
    	if (mcasp->chconstr[substream->stream].count)
    		snd_pcm_hw_constraint_list(substream->runtime,
    					   0, SNDRV_PCM_HW_PARAM_CHANNELS,
    					   &mcasp->chconstr[substream->stream]);
    
    	/*
    	 * If we rely on implicit BCLK divider setting we should
    	 * set constraints based on what we can provide.
    	 */
    	if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
    		int ret;
    
    		ruledata->mcasp = mcasp;
    
    		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
    					  SNDRV_PCM_HW_PARAM_RATE,
    					  davinci_mcasp_hw_rule_rate,
    					  ruledata,
    					  SNDRV_PCM_HW_PARAM_FORMAT, -1);
    		if (ret)
    			return ret;
    		ret = snd_pcm_hw_rule_add(substream->runtime, 0,
    					  SNDRV_PCM_HW_PARAM_FORMAT,
    					  davinci_mcasp_hw_rule_format,
    					  ruledata,
    					  SNDRV_PCM_HW_PARAM_RATE, -1);
    		if (ret)
    			return ret;
    	}
    
    	return 0;
    }
    
    static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
    				   struct snd_soc_dai *cpu_dai)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
    
    	mcasp->substreams[substream->stream] = NULL;
    
    	if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
    		return;
    
    	if (!cpu_dai->active)
    		mcasp->channels = 0;
    }
    
    static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
    	.startup	= davinci_mcasp_startup,
    	.shutdown	= davinci_mcasp_shutdown,
    	.trigger	= davinci_mcasp_trigger,
    	.hw_params	= davinci_mcasp_hw_params,
    	.set_fmt	= davinci_mcasp_set_dai_fmt,
    	.set_clkdiv	= davinci_mcasp_set_clkdiv,
    	.set_sysclk	= davinci_mcasp_set_sysclk,
    };
    
    static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
    
    	if (mcasp->version >= MCASP_VERSION_3) {
    		/* Using dmaengine PCM */
    		dai->playback_dma_data =
    				&mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
    		dai->capture_dma_data =
    				&mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
    	} else {
    		/* Using davinci-pcm */
    		dai->playback_dma_data = mcasp->dma_params;
    		dai->capture_dma_data = mcasp->dma_params;
    	}
    
    	return 0;
    }
    
    #ifdef CONFIG_PM_SLEEP
    static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
    	struct davinci_mcasp_context *context = &mcasp->context;
    	int i;
    	u32 reg;
    
    	context->pm_state = pm_runtime_active(mcasp->dev);
    	if (!context->pm_state)
    		pm_runtime_get_sync(mcasp->dev);
    
    	context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
    	context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
    	context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
    	context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
    	context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
    	context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
    	context->ahclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
    	context->ahclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG);
    	context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
    	context->rxmask = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXMASK_REG);
    	context->txmask = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXMASK_REG);
    	context->rxtdm = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXTDM_REG);
    	context->txtdm = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXTDM_REG);
    	if (mcasp->txnumevt) {
    		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
    		context->wfifoctl = mcasp_get_reg(mcasp, reg);
    	}
    	if (mcasp->rxnumevt) {
    		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
    		context->rfifoctl = mcasp_get_reg(mcasp, reg);
    	}
    	for (i = 0; i < mcasp->num_serializer; i++)
    		context->xrsrctl[i] = mcasp_get_reg(mcasp,
    						DAVINCI_MCASP_XRSRCTL_REG(i));
    
    	pm_runtime_put_sync(mcasp->dev);
    	return 0;
    }
    
    static int davinci_mcasp_resume(struct snd_soc_dai *dai)
    {
    	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
    	struct davinci_mcasp_context *context = &mcasp->context;
    	int i;
    	u32 reg;
    
    	pm_runtime_get_sync(mcasp->dev);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, context->ahclkxctl);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, context->ahclkrctl);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, context->rxmask);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, context->txmask);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, context->rxtdm);
    	mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, context->txtdm);
    	if (mcasp->txnumevt) {
    		reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
    		mcasp_set_reg(mcasp, reg, context->wfifoctl);
    	}
    	if (mcasp->rxnumevt) {
    		reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
    		mcasp_set_reg(mcasp, reg, context->rfifoctl);
    	}
    	for (i = 0; i < mcasp->num_serializer; i++)
    		mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
    			      context->xrsrctl[i]);
    
    	if (!context->pm_state)
    		pm_runtime_put_sync(mcasp->dev);
    
    	return 0;
    }
    #else
    #define davinci_mcasp_suspend NULL
    #define davinci_mcasp_resume NULL
    #endif
    
    #define DAVINCI_MCASP_RATES	SNDRV_PCM_RATE_8000_192000
    
    #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
    				SNDRV_PCM_FMTBIT_U8 | \
    				SNDRV_PCM_FMTBIT_S16_LE | \
    				SNDRV_PCM_FMTBIT_U16_LE | \
    				SNDRV_PCM_FMTBIT_S24_LE | \
    				SNDRV_PCM_FMTBIT_U24_LE | \
    				SNDRV_PCM_FMTBIT_S24_3LE | \
    				SNDRV_PCM_FMTBIT_U24_3LE | \
    				SNDRV_PCM_FMTBIT_S32_LE | \
    				SNDRV_PCM_FMTBIT_U32_LE)
    
    static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
    	{
    		.name		= "davinci-mcasp.0",
    		.probe		= davinci_mcasp_dai_probe,
    		.suspend	= davinci_mcasp_suspend,
    		.resume		= davinci_mcasp_resume,
    		.playback	= {
    			.channels_min	= 1,
    			.channels_max	= 32 * 16,
    			.rates 		= DAVINCI_MCASP_RATES,
    			.formats	= DAVINCI_MCASP_PCM_FMTS,
    		},
    		.capture 	= {
    			.channels_min	= 1,
    			.channels_max	= 32 * 16,
    			.rates 		= DAVINCI_MCASP_RATES,
    			.formats	= DAVINCI_MCASP_PCM_FMTS,
    		},
    		.ops 		= &davinci_mcasp_dai_ops,
    
    		.symmetric_samplebits	= 1,
    	},
    	{
    		.name		= "davinci-mcasp.1",
    		.probe		= davinci_mcasp_dai_probe,
    		.playback 	= {
    			.channels_min	= 1,
    			.channels_max	= 384,
    			.rates		= DAVINCI_MCASP_RATES,
    			.formats	= DAVINCI_MCASP_PCM_FMTS,
    		},
    		.ops 		= &davinci_mcasp_dai_ops,
    	},
    
    };
    
    static const struct snd_soc_component_driver davinci_mcasp_component = {
    	.name		= "davinci-mcasp",
    };
    
    /* Some HW specific values and defaults. The rest is filled in from DT. */
    static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
    	.tx_dma_offset = 0x400,
    	.rx_dma_offset = 0x400,
    	.asp_chan_q = EVENTQ_0,
    	.version = MCASP_VERSION_1,
    };
    
    static struct davinci_mcasp_pdata da830_mcasp_pdata = {
    	.tx_dma_offset = 0x2000,
    	.rx_dma_offset = 0x2000,
    	.asp_chan_q = EVENTQ_0,
    	.version = MCASP_VERSION_2,
    };
    
    static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
    	.tx_dma_offset = 0,
    	.rx_dma_offset = 0,
    	.asp_chan_q = EVENTQ_0,
    	.version = MCASP_VERSION_3,
    };
    
    static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
    	.tx_dma_offset = 0x200,
    	.rx_dma_offset = 0x284,
    	.asp_chan_q = EVENTQ_0,
    	.version = MCASP_VERSION_4,
    };
    
    static const struct of_device_id mcasp_dt_ids[] = {
    	{
    		.compatible = "ti,dm646x-mcasp-audio",
    		.data = &dm646x_mcasp_pdata,
    	},
    	{
    		.compatible = "ti,da830-mcasp-audio",
    		.data = &da830_mcasp_pdata,
    	},
    	{
    		.compatible = "ti,am33xx-mcasp-audio",
    		.data = &am33xx_mcasp_pdata,
    	},
    	{
    		.compatible = "ti,dra7-mcasp-audio",
    		.data = &dra7_mcasp_pdata,
    	},
    	{ /* sentinel */ }
    };
    MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
    
    static int mcasp_reparent_fck(struct platform_device *pdev)
    {
    	struct device_node *node = pdev->dev.of_node;
    	struct clk *gfclk, *parent_clk;
    	const char *parent_name;
    	int ret;
    
    	if (!node)
    		return 0;
    
    	parent_name = of_get_property(node, "fck_parent", NULL);
    	if (!parent_name)
    		return 0;
    
    	gfclk = clk_get(&pdev->dev, "fck");
    	if (IS_ERR(gfclk)) {
    		dev_err(&pdev->dev, "failed to get fck\n");
    		return PTR_ERR(gfclk);
    	}
    
    	parent_clk = clk_get(NULL, parent_name);
    	if (IS_ERR(parent_clk)) {
    		dev_err(&pdev->dev, "failed to get parent clock\n");
    		ret = PTR_ERR(parent_clk);
    		goto err1;
    	}
    
    	ret = clk_set_parent(gfclk, parent_clk);
    	if (ret) {
    		dev_err(&pdev->dev, "failed to reparent fck\n");
    		goto err2;
    	}
    
    err2:
    	clk_put(parent_clk);
    err1:
    	clk_put(gfclk);
    	return ret;
    }
    
    static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
    						struct platform_device *pdev)
    {
    	struct device_node *np = pdev->dev.of_node;
    	struct davinci_mcasp_pdata *pdata = NULL;
    	const struct of_device_id *match =
    			of_match_device(mcasp_dt_ids, &pdev->dev);
    	struct of_phandle_args dma_spec;
    
    	const u32 *of_serial_dir32;
    	u32 val;
    	int i, ret = 0;
    
    	if (pdev->dev.platform_data) {
    		pdata = pdev->dev.platform_data;
    		return pdata;
    	} else if (match) {
    		pdata = (struct davinci_mcasp_pdata*) match->data;
    	} else {
    		/* control shouldn't reach here. something is wrong */
    		ret = -EINVAL;
    		goto nodata;
    	}
    
    	ret = of_property_read_u32(np, "op-mode", &val);
    	if (ret >= 0)
    		pdata->op_mode = val;
    
    	ret = of_property_read_u32(np, "tdm-slots", &val);
    	if (ret >= 0) {
    		if (val < 2 || val > 32) {
    			dev_err(&pdev->dev,
    				"tdm-slots must be in rage [2-32]\n");
    			ret = -EINVAL;
    			goto nodata;
    		}
    
    		pdata->tdm_slots = val;
    	}
    
    	of_serial_dir32 = of_get_property(np, "serial-dir", &val);
    	val /= sizeof(u32);
    	if (of_serial_dir32) {
    		u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
    						 (sizeof(*of_serial_dir) * val),
    						 GFP_KERNEL);
    		if (!of_serial_dir) {
    			ret = -ENOMEM;
    			goto nodata;
    		}
    
    		for (i = 0; i < val; i++)
    			of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
    
    		pdata->num_serializer = val;
    		pdata->serial_dir = of_serial_dir;
    	}
    
    	if (pdata->version == MCASP_VERSION_4) {
    		for (i = 0; i < pdata->num_serializer; i++) {
    			if (pdata->serial_dir[i] == TX_MODE) {
    				pdata->tx_dma_offset =
    					DAVINCI_MCASP_TXBUF_REG(i);
    				break;
    			}
    		}
    
    		for (i = 0; i < pdata->num_serializer; i++) {
    			if (pdata->serial_dir[i] == RX_MODE) {
    				pdata->rx_dma_offset =
    					DAVINCI_MCASP_RXBUF_REG(i);
    				break;
    			}
    		}
    	}
    
    	ret = of_property_match_string(np, "dma-names", "tx");
    	if (ret < 0)
    		goto nodata;
    
    	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
    					 &dma_spec);
    	if (ret < 0)
    		goto nodata;
    
    	pdata->tx_dma_channel = dma_spec.args[0];
    
    	ret = of_property_match_string(np, "dma-names", "rx");
    	if (ret < 0)
    		goto nodata;
    
    	ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
    					 &dma_spec);
    	if (ret < 0)
    		goto nodata;
    
    	pdata->rx_dma_channel = dma_spec.args[0];
    
    	ret = of_property_read_u32(np, "tx-num-evt", &val);
    	if (ret >= 0)
    		pdata->txnumevt = val;
    
    	ret = of_property_read_u32(np, "rx-num-evt", &val);
    	if (ret >= 0)
    		pdata->rxnumevt = val;
    
    	ret = of_property_read_u32(np, "sram-size-playback", &val);
    	if (ret >= 0)
    		pdata->sram_size_playback = val;
    
    	ret = of_property_read_u32(np, "sram-size-capture", &val);
    	if (ret >= 0)
    		pdata->sram_size_capture = val;
    
    	if (of_find_property(np, "shared-dai", NULL))
    		pdata->shared_dai = 1;
    	else
    		pdata->shared_dai = 0;
    
    	return  pdata;
    
    nodata:
    	if (ret < 0) {
    		dev_err(&pdev->dev, "Error populating platform data, err %d\n",
    			ret);
    		pdata = NULL;
    	}
    	return  pdata;
    }
    
    /* All serializers must have equal number of channels */
    static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp,
    				       struct snd_pcm_hw_constraint_list *cl,
    				       int serializers)
    {
    	unsigned int *list;
    	int i, count = 0;
    
    	if (serializers <= 1)
    		return 0;
    
    	list = devm_kzalloc(mcasp->dev, sizeof(unsigned int) *
    			    (mcasp->tdm_slots + serializers - 1),
    			    GFP_KERNEL);
    	if (!list)
    		return -ENOMEM;
    
    	for (i = 1; i <= mcasp->tdm_slots; i++)
    		list[count++] = i;
    
    	for (i = 2; i <= serializers; i++)
    		list[count++] = i*mcasp->tdm_slots;
    
    	cl->count = count;
    	cl->list = list;
    
    	return 0;
    }
    
    
    static int davinci_mcasp_init_ch_constraints(struct davinci_mcasp *mcasp)
    {
    	int rx_serializers = 0, tx_serializers = 0, ret, i;
    
    	for (i = 0; i < mcasp->num_serializer; i++)
    		if (mcasp->serial_dir[i] == TX_MODE)
    			tx_serializers++;
    		else if (mcasp->serial_dir[i] == RX_MODE)
    			rx_serializers++;
    
    	ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[
    						  SNDRV_PCM_STREAM_PLAYBACK],
    					  tx_serializers);
    	if (ret)
    		return ret;
    
    	ret = davinci_mcasp_ch_constraint(mcasp, &mcasp->chconstr[
    						  SNDRV_PCM_STREAM_CAPTURE],
    					  rx_serializers);
    
    	return ret;
    }
    
    #if IS_ENABLED(CONFIG_DISPLAY_DRA7EVM_ENCODER_TPD12S015)
    #define DRA7_MCASP_HDMI_SEL_GPIO	(1 << 2)
    int dra7_mcasp_hdmi_gpio_get(struct platform_device *pdev)
    {
    	struct davinci_mcasp *mcasp;
    
    	if (!pdev)
    		return -EPROBE_DEFER;
    
    	mcasp = dev_get_drvdata(&pdev->dev);
    	if (!mcasp)
    		return -EPROBE_DEFER;
    
    	if (!mcasp->is_mcasp8)
    		return 0;
    
    	pm_runtime_get_sync(mcasp->dev);
    
    	/* First set the direction to output */
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
    		       DRA7_MCASP_HDMI_SEL_GPIO);
    	/* then set the PDOUT */
    	if (mcasp->hdmi_sel_gpio)
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG,
    			       DRA7_MCASP_HDMI_SEL_GPIO);
    	else
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG,
    			       DRA7_MCASP_HDMI_SEL_GPIO);
    	/* at last, change the function to GPIO mode */
    	mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG,
    		       DRA7_MCASP_HDMI_SEL_GPIO);
    
    	return 0;
    }
    EXPORT_SYMBOL(dra7_mcasp_hdmi_gpio_get);
    
    int dra7_mcasp_hdmi_gpio_put(struct platform_device *pdev)
    {
    	struct davinci_mcasp *mcasp;
    
    	if (!pdev)
    		return -EPROBE_DEFER;
    
    	mcasp = dev_get_drvdata(&pdev->dev);
    	if (!mcasp)
    		return -EPROBE_DEFER;
    
    	if (!mcasp->is_mcasp8)
    		return 0;
    
    	/* Set the pin as McASP pin */
    	mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG,
    		       DRA7_MCASP_HDMI_SEL_GPIO);
    
    	pm_runtime_put_sync(mcasp->dev);
    
    	return 0;
    }
    EXPORT_SYMBOL(dra7_mcasp_hdmi_gpio_put);
    
    int dra7_mcasp_hdmi_gpio_set(struct platform_device *pdev, bool high)
    {
    	struct davinci_mcasp *mcasp;
    
    	if (!pdev)
    		return -EPROBE_DEFER;
    
    	mcasp = dev_get_drvdata(&pdev->dev);
    	if (!mcasp)
    		return -EPROBE_DEFER;
    
    	if (!mcasp->is_mcasp8)
    		return 0;
    
    	if (!pm_runtime_active(mcasp->dev)) {
    		dev_warn(mcasp->dev, "mcasp8 is not enabled!\n");
    		return -ENODEV;
    	}
    
    	if (mcasp->hdmi_sel_gpio == high)
    		return 0;
    
    	mcasp->hdmi_sel_gpio = high;
    	if (mcasp->hdmi_sel_gpio)
    		mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG,
    			       DRA7_MCASP_HDMI_SEL_GPIO);
    	else
    		mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG,
    			       DRA7_MCASP_HDMI_SEL_GPIO);
    
    	return 0;
    }
    EXPORT_SYMBOL(dra7_mcasp_hdmi_gpio_set);
    #endif /* CONFIG_DISPLAY_DRA7EVM_ENCODER_TPD12S015 */
    
    static int davinci_mcasp_probe(struct platform_device *pdev)
    {
    	struct davinci_pcm_dma_params *dma_params;
    	struct snd_dmaengine_dai_dma_data *dma_data;
    	struct resource *mem, *ioarea, *res, *dat;
    	struct davinci_mcasp_pdata *pdata;
    	struct davinci_mcasp *mcasp;
    	int irq;
    	int ret;
    
    	if (!pdev->dev.platform_data && !pdev->dev.of_node) {
    		dev_err(&pdev->dev, "No platform data supplied\n");
    		return -EINVAL;
    	}
    
    	mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
    			   GFP_KERNEL);
    	if (!mcasp)
    		return	-ENOMEM;
    
    	pdata = davinci_mcasp_set_pdata_from_of(pdev);
    	if (!pdata) {
    		dev_err(&pdev->dev, "no platform data\n");
    		return -EINVAL;
    	}
    
    	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
    	if (!mem) {
    		dev_warn(mcasp->dev,
    			 "\"mpu\" mem resource not found, using index 0\n");
    		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    		if (!mem) {
    			dev_err(&pdev->dev, "no mem resource?\n");
    			return -ENODEV;
    		}
    	}
    
    #if IS_ENABLED(CONFIG_DISPLAY_DRA7EVM_ENCODER_TPD12S015)
    	if (pdata->version == MCASP_VERSION_4 && mem->start == 0x4847c000)
    		mcasp->is_mcasp8 = true;
    #endif
    	ioarea = devm_request_mem_region(&pdev->dev, mem->start,
    			resource_size(mem), pdev->name);
    	if (!ioarea) {
    		dev_err(&pdev->dev, "Audio region already claimed\n");
    		return -EBUSY;
    	}
    
    	pm_runtime_enable(&pdev->dev);
    
    	/*
    	 * Forbid runtime PM if the DAI is shared, data transfers will occur
    	 * from a different core (typically DSP).
    	 */
    	if (pdata->shared_dai) {
    		dev_info(&pdev->dev, "DAI is shared\n");
    		pm_runtime_forbid(&pdev->dev);
    	}
    
    	mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
    	if (!mcasp->base) {
    		dev_err(&pdev->dev, "ioremap failed\n");
    		ret = -ENOMEM;
    		goto err;
    	}
    
    	mcasp->op_mode = pdata->op_mode;
    	/* sanity check for tdm slots parameter */
    	if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
    		if (pdata->tdm_slots < 2) {
    			dev_err(&pdev->dev, "invalid tdm slots: %d\n",
    				pdata->tdm_slots);
    			mcasp->tdm_slots = 2;
    		} else if (pdata->tdm_slots > 32) {
    			dev_err(&pdev->dev, "invalid tdm slots: %d\n",
    				pdata->tdm_slots);
    			mcasp->tdm_slots = 32;
    		} else {
    			mcasp->tdm_slots = pdata->tdm_slots;
    		}
    	}
    
    	mcasp->num_serializer = pdata->num_serializer;
    #ifdef CONFIG_PM_SLEEP
    	mcasp->context.xrsrctl = devm_kzalloc(&pdev->dev,
    					sizeof(u32) * mcasp->num_serializer,
    					GFP_KERNEL);
    #endif
    	mcasp->serial_dir = pdata->serial_dir;
    	mcasp->version = pdata->version;
    	mcasp->txnumevt = pdata->txnumevt;
    	mcasp->rxnumevt = pdata->rxnumevt;
    
    	mcasp->dev = &pdev->dev;
    
    	irq = platform_get_irq_byname(pdev, "rx");
    	if (irq >= 0) {
    		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
    				davinci_mcasp_rx_irq_handler,
    				IRQF_ONESHOT, dev_name(&pdev->dev), mcasp);
    		if (ret) {
    			dev_err(&pdev->dev, "RX IRQ request failed\n");
    			goto err;
    		}
    	}
    
    	irq = platform_get_irq_byname(pdev, "tx");
    	if (irq >= 0) {
    		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
    				davinci_mcasp_tx_irq_handler,
    				IRQF_ONESHOT, dev_name(&pdev->dev), mcasp);
    		if (ret) {
    			dev_err(&pdev->dev, "TX IRQ request failed\n");
    			goto err;
    		}
    	}
    
    	dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
    	if (dat)
    		mcasp->dat_port = true;
    
    	dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
    	dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
    	dma_params->asp_chan_q = pdata->asp_chan_q;
    	dma_params->ram_chan_q = pdata->ram_chan_q;
    	dma_params->sram_pool = pdata->sram_pool;
    	dma_params->sram_size = pdata->sram_size_playback;
    	if (dat)
    		dma_params->dma_addr = dat->start;
    	else
    		dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
    
    	/* Unconditional dmaengine stuff */
    	dma_data->addr = dma_params->dma_addr;
    
    	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
    	if (res)
    		dma_params->channel = res->start;
    	else
    		dma_params->channel = pdata->tx_dma_channel;
    
    	/* dmaengine filter data for DT and non-DT boot */
    	if (pdev->dev.of_node)
    		dma_data->filter_data = "tx";
    	else
    		dma_data->filter_data = &dma_params->channel;
    
    	dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
    	dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
    	dma_params->asp_chan_q = pdata->asp_chan_q;
    	dma_params->ram_chan_q = pdata->ram_chan_q;
    	dma_params->sram_pool = pdata->sram_pool;
    	dma_params->sram_size = pdata->sram_size_capture;
    	if (dat)
    		dma_params->dma_addr = dat->start;
    	else
    		dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
    
    	/* Unconditional dmaengine stuff */
    	dma_data->addr = dma_params->dma_addr;
    
    	if (mcasp->version < MCASP_VERSION_3) {
    		mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
    		/* dma_params->dma_addr is pointing to the data port address */
    		mcasp->dat_port = true;
    	} else {
    		mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
    	}
    
    	res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
    	if (res)
    		dma_params->channel = res->start;
    	else
    		dma_params->channel = pdata->rx_dma_channel;
    
    	/* dmaengine filter data for DT and non-DT boot */
    	if (pdev->dev.of_node)
    		dma_data->filter_data = "rx";
    	else
    		dma_data->filter_data = &dma_params->channel;
    
    	ret = davinci_mcasp_init_ch_constraints(mcasp);
    	if (ret)
    		goto err;
    
    	dev_set_drvdata(&pdev->dev, mcasp);
    
    	mcasp_reparent_fck(pdev);
    
    	if (mcasp->version == MCASP_VERSION_4) {
    		pm_runtime_get_sync(mcasp->dev);
    		mcasp->revision = mcasp_get_reg(mcasp, DAVINCI_MCASP_PID_REG) &
    					MCASP_V4_REVISION_MASK;
    		pm_runtime_put(mcasp->dev);
    	}
    
    	/*
    	 * FIFO events to eDMA or sDMA can be lost depending on the
    	 * timing between McASP side activity and DMA side activity,
    	 * causing overflow (capture) or underflow (playback).
    	 * The workaround consists of maximizing the time to avoid
    	 * the boundary condition in hardware.
    	 */
    	if ((mcasp->version == MCASP_VERSION_4) &&
    	    (mcasp->revision < MCASP_V4_REVISION(3, 3))) {
    		if (mcasp->txnumevt || mcasp->rxnumevt)
    			dev_info(&pdev->dev,
    				 "numevt will be ignored due to errata i868\n");
    
    		if (mcasp->txnumevt)
    			mcasp->txnumevt = 32;
    		if (mcasp->rxnumevt)
    			mcasp->rxnumevt = 32;
    	}
    
    	ret = devm_snd_soc_register_component(&pdev->dev,
    					&davinci_mcasp_component,
    					&davinci_mcasp_dai[pdata->op_mode], 1);
    
    	if (ret != 0)
    		goto err;
    
    	switch (mcasp->version) {
    #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \
    	(IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
    	 IS_MODULE(CONFIG_SND_DAVINCI_SOC))
    	case MCASP_VERSION_1:
    	case MCASP_VERSION_2:
    		ret = davinci_soc_platform_register(&pdev->dev);
    		break;
    #endif
    #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \
    	(IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
    	 IS_MODULE(CONFIG_SND_EDMA_SOC))
    	case MCASP_VERSION_3:
    		ret = edma_pcm_platform_register(&pdev->dev);
    		break;
    #endif
    #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \
    	(IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \
    	 IS_MODULE(CONFIG_SND_OMAP_SOC))
    	case MCASP_VERSION_4:
    		ret = edma_pcm_platform_register(&pdev->dev);
    		if (ret) {
    			dev_err(&pdev->dev, "register eDMA PCM failed: %d\n",
    				ret);
    			goto err;
    		}
    
    		ret = omap_pcm_platform_register(&pdev->dev);
    		break;
    #endif
    	default:
    		dev_err(&pdev->dev, "Invalid McASP version: %d\n",
    			mcasp->version);
    		ret = -EINVAL;
    		break;
    	}
    
    	if (ret) {
    		dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
    		goto err;
    	}
    
    	return 0;
    
    err:
    	pm_runtime_disable(&pdev->dev);
    	return ret;
    }
    
    static int davinci_mcasp_remove(struct platform_device *pdev)
    {
    	pm_runtime_disable(&pdev->dev);
    
    	return 0;
    }
    
    static struct platform_driver davinci_mcasp_driver = {
    	.probe		= davinci_mcasp_probe,
    	.remove		= davinci_mcasp_remove,
    	.driver		= {
    		.name	= "davinci-mcasp",
    		.owner	= THIS_MODULE,
    		.of_match_table = mcasp_dt_ids,
    	},
    };
    
    module_platform_driver(davinci_mcasp_driver);
    
    MODULE_AUTHOR("Steve Chen");
    MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
    MODULE_LICENSE("GPL");
    

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

    -

    -

    -

    Since you mentioned that the audio link between the two McASP instances is I2S, that's technically a stereo link. I mentioned the bt-sco as an example of a dummy codec. If the bt-sco doesn't meet your sample rate or channel reqs, then you may need to create your own dummy driver.

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

    [Louis] I regenerate a 1k tone with 8k sampling rate, but it still cannot work after patching

    -

    -

    root@wnc-cb:~# aplay -D hw:0 output.wav
    Playing WAVE 'output.wav' : Signed 32 bit Little Endian, Rate 8000 Hz, Mono
    aplay: set_params:1204: Broken configuration for this PCM: no configurations available
    root@wnc-cb:~#
    root@wnc-cb:~#

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

    -

    -

    -

    Also, the hw_params in your logs seem to indicate that this link is not precisely for SCO but to for A2DP. Please confirm. If so, the bt-sco is not the right codec for your usecase.

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

    [Louis] I use 1k tone with sampling rate 8k

    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------

    -

    -

    -

    The following information are drivers I used:

    @ Simple Sound Card driver instead of dra7xx-jamr3-card.c and davinci-evm.c.

    @ bt-sco codec driver

    @ davinci-mcasp driver

    -

    -

    -

    I attached my boot log

    Carrier Board GLSDK 7.02.00.02.txt
    U-Boot SPL 2014.07 (Jun 27 2017 - 19:20:34)
    DRA752-GP ES1.1
    before do_io_settings
    before prcm_init
            |-before enable_basic_clocks
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
    Enable clock module - 4a008728
    Enable clock module - 4a008b30
    Enable clock module - 4a008b38
    Enable clock module - 4a008d20
    Enable clock module - 4ae07838
    Enable clock module - 4a009760
    Enable clock module - 4a009768
    Enable clock module - 4a009770
    Enable clock module - 4a009778
    Enable clock module - 4a009780
    Enable clock module - 4a009810
    Enable clock module - 4a009818
    Enable clock module - 4a008778
    Enable clock module - 4a008780
    Enable clock module - 4ae07840
    Enable clock module - 4a009328
    Enable clock module - 4a009330
    Enable clock module - 4a009738
    Enable clock module - 4ae07830
    Enable clock module - 4a009850
    Enable clock module - 4a0097a0
    Enable clock module - 4a0093d0
    Enable clock module - 4a009838
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
            |-before timer_init
            |-before scale_vcores
                    |-before vcores->core
    optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1030, using efuse value 970
                    |-before core
    do_scale_vcore: volt - 970 offset_code - 0x35
                    |-before recalibrate_iodelay
    KEEP 6_30(ETH_SEL) input
    switch to NVA_SDIO (6_29 input).....
    switch to HDMI_I2C_SEL (6_12 input).....
    Power off LGA Board....
                            |-before __recalibrate_iodelay
                                    |-before calibrate_iodelay
                                    |-before isolate_io
                                            |- isolate = 1
                                            |-  wait_on_value1CBBBBB�Kwait_on_value2
    IODELAY: IO delay recalibration successfully completed
                    |-before vcores->mpu
    optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=1090, using efuse value 985
                    |-before mpu
    do_scale_vcore: volt - 985 offset_code - 0x37
                    |-before abb_setup
                    |-before mm
                    |-before mm
                    |-before gpu
    optimize_vcore_voltage:efuse 0x4a003b10 bits=16 Vnom=1250, using efuse value 1060
                    |-before gpu
    do_scale_vcore: volt - 1060 offset_code - 0x3e
                    |-before eve
    optimize_vcore_voltage:efuse 0x4a0025e0 bits=16 Vnom=1060, using efuse value 965
                    |-before eve
    do_scale_vcore: volt - 965 offset_code - 0x35
                    |-before iva
    optimize_vcore_voltage:efuse 0x4a0025cc bits=16 Vnom=1060, using efuse value 970
                    |-before iva
    do_scale_vcore: volt - 970 offset_code - 0x35
     |-before setup_dplls
    setup_dplls
    
     core Dpll locked, but not for ideal M = 277,N = 4 values, current values are M = 1330,N= 23
     before core[4a005120] Dpll wait_for_lock
    Core DPLL configured
    
     per Dpll locked, but not for ideal M = 20,N = 0 values, current values are M = 1280,N= ��j�I��KW$�Y?MX8140] Dpll wait_for_lock
    PER DPLL locked
    
     mpu Dpll locked, but not for ideal M = 625,N = 11 values, current values are M = 1470,N= 23
     before mpu[4a005160] Dpll wait_for_lock
    MPU DPLL locked
    
     before usb[4a008180] Dpll wait_for_lock
    
     before ddr[4a005210] Dpll wait_for_lock
    
     before gmac[4a0052a8] Dpll wait_for_lock
     |-before setup_warmreset_time
    before board_early_init_f
    before sdram_init
    >>sdram_init()
    in_sdram = 0
    >>do_sdram_init() 4c000000
    <<do_sdram_init() 4c000000
     size_prog = 20000000
    base=80000000 , maxsize=20000000 , cnt=8000000
    i=27
    get_ram_size() successful<<sdram_init()
    spl_mmc_load_image
    reading dra7-evm.dtb
    spl_load_image_fat_os: error reading image dra7-evm.dtb, err - -1
    reading u-boot.img
    reading u-boot.img
    before init_omap_revision
    before hw_data_init
    before watchdog_init
    before set_mux_conf_regs
    before prcm_init
    
    
    U-Boot 2014.07 (Jun 27 2017 - 19:20:34)
    
    CPU  : DRA752-GP ES1.1
    Board: DRA7xx
    I2C:   ready
    DRAM:  >>sdram_init()
    512 MiB
    NAND:  0 MiB
    MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
    *** Error - No Valid Environment Area found
    *** Warning - bad CRC, using default environment
    
    serial# not set, setting...
    SATA link 0 timeout.
    AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
    flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
    scanning bus for devices...
    Found 0 device(s).
    SCSI:  Net:   cpsw
    Hit any key to stop autoboot:  0
    U-Boot#
    U-Boot#
    U-Boot#
    U-Boot# pwr_on_j6_sd
    Turn on SATA
    SATA SEL
    Turn on ULPI
    Turn on PCIE
    Turn the 6165 and 1512 on.....
    U-Boot# run boot_cb
    ==== This is CB Ver.F =====
    switch to partitions #0, OK
    mmc0 is current device
    SD/MMC found on device 0
    reading uEnv.txt
    221 bytes read in 4 ms (53.7 KiB/s)
    Loaded environment from uEnv.txt
    Importing environment from mmc0 ...
    5125536 bytes read in 448 ms (10.9 MiB/s)
    101543 bytes read in 31 ms (3.1 MiB/s)
    Booting from mmc0 ...
    Kernel image @ 0x82000000 [ 0x000000 - 0x4e35a0 ]
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffe4000, end 8ffffca6 ... OK
    
    Starting kernel ...
    
    
    Starting kernel 4
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 3.14.49 (root@louis-VirtualBox) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #69 SMP PREEMPT Thu Jun 29 10:42:27 CST 2017
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] Machine model: TI DRA742
    [    0.000000] Reserved memory: created CMA memory pool at 0x95800000, size 56 MiB
    [    0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 64 MiB
    [    0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9d000000, size 32 MiB
    [    0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9f000000, size 8 MiB
    [    0.000000] Reserved memory: initialized node dsp2_cma@9f000000, compatible id shared-dma-pool
    [    0.000000] cma: CMA: reserved 64 MiB at 91000000
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] DRA752 ES1.1
    [    0.000000] PERCPU: Embedded 8 pages/cpu @dfa49000 s8640 r8192 d15936 u32768
    [    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 128768
    [    0.000000] Kernel command line: console=ttyO2,115200n8 elevator=noop root=PARTUUID=ad201e1b-02 rw rootwait earlyprintk fixrtc omapdrm.num_crtc=2 consoleblank=0 cma=64M rootfstype=ext4 snd.slots_reserved=1,1
    [    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
    [    0.000000] Memory: 273800K/519168K available (6675K kernel code, 689K rwdata, 2644K rodata, 376K init, 266K bss, 245368K reserved, 0K highmem)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    [    0.000000]     vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0xc0008000 - 0xc09220cc   (9321 kB)
    [    0.000000]       .init : 0xc0923000 - 0xc09811c0   ( 377 kB)
    [    0.000000]       .data : 0xc0982000 - 0xc0a2e520   ( 690 kB)
    [    0.000000]        .bss : 0xc0a2e52c - 0xc0a7103c   ( 267 kB)
    [    0.000000] Preemptible hierarchical RCU implementation.
    [    0.000000] NR_IRQS:16 nr_irqs:16 16
    [    0.000000] OMAP clockevent source: timer1 at 31475 Hz
    [    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns
    [    0.000030] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000396] Architected cp15 timer(s) running at 5.90MHz (virt).
    [    0.000432] sched_clock: 56 bits at 5MHz, resolution 169ns, wraps every 2911033065472ns
    [    0.000440] Switching to timer-based delay loop
    [    0.001456] Console: colour dummy device 80x30
    [    0.001475] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
    [    0.001482] This ensures that you still see kernel messages. Please
    [    0.001488] update your kernel commandline.
    [    0.001501] Calibrating delay loop (skipped), value calculated using timer frequency.. 11.80 BogoMIPS (lpj=59016)
    [    0.001513] pid_max: default: 32768 minimum: 301
    [    0.001623] Security Framework initialized
    [    0.001676] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.001686] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.025918] CPU: Testing write buffer coherency: ok
    [    0.026180] /cpus/cpu@0 missing clock-frequency property
    [    0.026217] /cpus/cpu@1 missing clock-frequency property
    [    0.026229] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.026256] Setting up static identity map for 0x8068a628 - 0x8068a698
    [    0.080824] CPU1: Booted secondary processor
    [    0.080853] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.080979] Brought up 2 CPUs
    [    0.080995] SMP: Total of 2 processors activated (23.60 BogoMIPS).
    [    0.081002] CPU: All CPU(s) started in SVC mode.
    [    0.081425] devtmpfs: initialized
    [    0.082172] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.083896] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.097360] omap_hwmod: tptc0 using broken dt data from edma-controller
    [    0.097876] omap_hwmod: tptc1 using broken dt data from edma-controller
    [    0.269506] pinctrl core: initialized pinctrl subsystem
    [    0.270261] regulator-dummy: no parameters
    [    0.274656] NET: Registered protocol family 16
    [    0.276540] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.278621] cpuidle: using governor ladder
    [    0.278632] cpuidle: using governor menu
    [    0.325488] syscon 4a002000.tisysconcore: regmap [mem 0x4a002000-0x4a0026cf] registered
    [    0.325821] syscon 4a002e00.tisyscon: regmap [mem 0x4a002e00-0x4a002e7b] registered
    [    0.328671] OMAP GPIO hardware version 0.1
    [    0.335093] irq: no irq domain found for /ocp/pinmux@4a003400 !
    [    0.342605] platform 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000
    [    0.342911] platform 55020000.ipu: assigned reserved memory node ipu2_cma@95800000
    [    0.343210] platform 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
    [    0.358963] platform 41000000.dsp: assigned reserved memory node dsp2_cma@9f000000
    [    0.363953] No ATAGs?
    [    0.363980] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
    [    0.363990] hw-breakpoint: maximum watchpoint size is 8 bytes.
    [    0.366914] OMAP DMA hardware revision 0.0
    [    0.394534] bio: create slab <bio-0> at 0
    [    0.409761] edma-dma-engine edma-dma-engine.0: TI EDMA DMA engine driver
    [    0.416547] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver
    [    0.417355] evm_3v3_sd: 3300 mV
    [    0.417670] evm_3v3_sw: 3300 mV
    [    0.417738] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to find supply vin
    [    0.417926] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to register regulator: -517
    [    0.417945] platform fixedregulator-evm_3v3_sw: Driver reg-fixed-voltage requests probe deferral
    [    0.418199] aic_dvdd: 1800 mV
    [    0.418259] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to find supply vin
    [    0.418437] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to register regulator: -517
    [    0.418456] platform fixedregulator-aic_dvdd: Driver reg-fixed-voltage requests probe deferral
    [    0.418707] vmmcwl_fixed: 1800 mV
    [    0.419025] vtt_fixed: 1350 mV
    [    0.419070] reg-fixed-voltage fixedregulator-vtt: Failed to find supply vin
    [    0.419248] reg-fixed-voltage fixedregulator-vtt: Failed to register regulator: -517
    [    0.419267] platform fixedregulator-vtt: Driver reg-fixed-voltage requests probe deferral
    [    0.422812] vgaarb: loaded
    [    0.423266] i2c-core: driver [palmas] using legacy suspend method
    [    0.423275] i2c-core: driver [palmas] using legacy resume method
    [    0.423876] SCSI subsystem initialized
    [    0.425166] usbcore: registered new interface driver usbfs
    [    0.425332] usbcore: registered new interface driver hub
    [    0.425516] usbcore: registered new device driver usb
    [    0.427860] palmas 0-0058: IRQ missing: skipping irq request
    [    0.428215] palmas 0-0058: Muxing GPIO a, PWM 0, LED 0
    [    0.428363] prom_parse: Bad cell count for /ocp/i2c@48070000/tps659038@58
    [    0.430550] smps12: 850 <--> 1250 mV at 990 mV
    [    0.433800] smps3: 850 <--> 1250 mV at 1350 mV
    [    0.435501] smps45: 850 <--> 1150 mV at 970 mV
    [    0.437187] smps6: 850 <--> 1250 mV at 1060 mV
    [    0.438722] smps7: 850 <--> 1060 mV at 970 mV
    [    0.440410] smps8: 850 <--> 1250 mV at 970 mV
    [    0.441975] smps9: 1800 mV
    [    0.451722] ldo1: 1800 <--> 3300 mV at 3000 mV
    [    0.461105] ldo2: 3300 mV
    [    0.471187] ldo3: 1800 mV
    [    0.472094] LDO4: no parameters
    [    0.472686] LDO5: no parameters
    [    0.473292] LDO6: no parameters
    [    0.473898] LDO7: no parameters
    [    0.474499] LDO8: no parameters
    [    0.481133] ldo9: 1050 mV
    [    0.491158] ldoln: 1800 mV
    [    0.501220] ldousb: 3300 mV
    [    0.502122] regen1: no parameters
    [    0.502709] regen2: no parameters
    [    0.503417] sysen1: no parameters
    [    0.504024] sysen2: no parameters
    [    0.504282] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
    [    0.506261] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
    [    0.506331] omap_i2c 4807a000.i2c: could not find pctldev for node /ocp/padconf@4844a000/pinmux_i2c4_pins, deferring probe
    [    0.506347] platform 4807a000.i2c: Driver omap_i2c requests probe deferral
    [    0.506773] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
    [    0.507063] media: Linux media interface: v0.10
    [    0.507216] Linux video capture interface: v2.00
    [    0.507442] pps_core: LinuxPPS API ver. 1 registered
    [    0.507450] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [    0.507569] PTP clock support registered
    [    0.509048] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
    [    0.509512] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
    [    0.510551] omap-iommu 40d01000.mmu: 40d01000.mmu registered
    [    0.510659] omap-iommu 40d02000.mmu: 40d02000.mmu registered
    [    0.510762] omap-iommu 58882000.mmu: 58882000.mmu registered
    [    0.510900] omap-iommu 55082000.mmu: 55082000.mmu registered
    [    0.511070] omap-iommu 41501000.mmu: 41501000.mmu registered
    [    0.511181] omap-iommu 41502000.mmu: 41502000.mmu registered
    [    0.511951] Advanced Linux Sound Architecture Driver Initialized.
    [    0.513353] Switched to clocksource arch_sys_counter
    [    0.531911] NET: Registered protocol family 2
    [    0.532599] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
    [    0.532639] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
    [    0.532709] TCP: Hash tables configured (established 4096 bind 4096)
    [    0.532750] TCP: reno registered
    [    0.532762] UDP hash table entries: 256 (order: 1, 8192 bytes)
    [    0.532783] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
    [    0.532969] NET: Registered protocol family 1
    [    0.533234] RPC: Registered named UNIX socket transport module.
    [    0.533244] RPC: Registered udp transport module.
    [    0.533251] RPC: Registered tcp transport module.
    [    0.533258] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [    0.534412] hw perfevents: enabled with ARMv7 Cortex-A15 PMU driver, 7 counters available
    [    0.537350] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.648602] VFS: Disk quotas dquot_6.5.2
    [    0.648710] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
    [    0.649302] NFS: Registering the id_resolver key type
    [    0.649343] Key type id_resolver registered
    [    0.649352] Key type id_legacy registered
    [    0.649385] jffs2: version 2.2. (NAND) (SUMMARY)  c 2001-2006 Red Hat, Inc.
    [    0.649568] msgmni has been set to 982
    [    0.653477] alg: No test for stdrng (krng)
    [    0.653658] NET: Registered protocol family 38
    [    0.653688] io scheduler noop registered (default)
    [    0.653697] io scheduler deadline registered
    [    0.653730] io scheduler cfq registered
    [    0.659915] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
    [    0.698714] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
    [    0.698729] pci_bus 0000:00: root bus resource [io  0x1000-0x10000]
    [    0.698740] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
    [    0.698752] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
    [    0.699275] PCI: bus0: Fast back to back transfers disabled
    [    0.699521] PCI: bus1: Fast back to back transfers enabled
    [    0.699638] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
    [    0.699654] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
    [    0.699667] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.699687] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.703600] pbias_mmc_omap5: 1800 <--> 3000 mV at 3000 mV
    [    0.704402] abb_mpu: 1100 <--> 1210 mV
    [    0.704755] abb_ivahd: 1060 <--> 1250 mV
    [    0.705111] abb_dspeve: 1060 <--> 1250 mV
    [    0.705461] abb_gpu: 1060 <--> 1280 mV
    [    0.706572] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
    [    0.711037] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 299, base_baud = 3000000) is a 8250
    [    0.711826] 4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 300, base_baud = 3000000) is a 8250
    [    0.712591] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 301, base_baud = 3000000) is a 8250
    [    1.860155] console [ttyS2] enabled
    [    1.864482] 48066000.serial: ttyS4 at MMIO 0x48066000 (irq = 302, base_baud = 3000000) is a 8250
    [    1.874167] 48420000.serial: ttyS6 at MMIO 0x48420000 (irq = 303, base_baud = 3000000) is a 8250
    [    1.884775] omap_rng 48090000.rng: OMAP Random Number Generator ver. 20
    [    1.891929] [drm] Initialized drm 1.1.0 20060810
    [    1.907213] brd: module loaded
    [    1.915842] loop: module loaded
    [    1.919326] (hci_tty): inside hci_tty_init
    [    1.923806] (hci_tty): allocated 249, 0
    [    1.930087] ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
    [    1.936856] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
    [    1.945437] ahci 4a140000.sata: flags: 64bit ncq sntf stag pm led clo only pmp pio slum part ccc apst
    [    1.955929] scsi0 : ahci_platform
    [    1.959732] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 336
    [    1.969019] mtdoops: mtd device (mtddev=name/number) must be supplied
    [    1.980853] usbcore: registered new interface driver asix
    [    1.986445] usbcore: registered new interface driver ax88179_178a
    [    1.992704] usbcore: registered new interface driver cdc_ether
    [    1.998744] usbcore: registered new interface driver smsc95xx
    [    2.004674] usbcore: registered new interface driver net1080
    [    2.010497] usbcore: registered new interface driver cdc_subset
    [    2.016597] usbcore: registered new interface driver zaurus
    [    2.022368] usbcore: registered new interface driver cdc_ncm
    [    2.028494] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    [    2.035067] ehci-pci: EHCI PCI platform driver
    [    2.039677] ehci-omap: OMAP-EHCI Host Controller driver
    [    2.045473] usbcore: registered new interface driver cdc_wdm
    [    2.051319] usbcore: registered new interface driver usb-storage
    [    2.058454] mousedev: PS/2 mouse device common for all mice
    [    2.066202] i2c-core: driver [rtc-ds1307] using legacy suspend method
    [    2.072670] i2c-core: driver [rtc-ds1307] using legacy resume method
    [    2.079742] omap_rtc 48838000.rtcss: rtc core: registered 48838000.rtcss as rtc0
    [    2.088057] i2c /dev entries driver
    [    2.092592] tvp5158 1-0058: i2c i/o error: rc == -121 (should be 1)
    [    2.098996] tvp5158 1-0058: i2c i/o error: rc == -121 (should be 1)
    [    2.105494] tvp5158 1-0058: ERROR: Chip id is not TVP5158
    [    2.111848] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
    [    2.117990] vip 48970000.vip: No explicit pinctrl resources data.
    [    2.125070] vip 48970000.vip: loading firmware vpdma-1b8.bin
    [    2.131001] Driver for 1-wire Dallas network protocol.
    [    2.136502] vpe 489d0000.vpe: Device registered as /dev/video0
    [    2.143322] coproc iva_coproc: probe
    [    2.146943] vip 48970000.vip: VPDMA firmware loaded
    [    2.151958] vip1-s1: Port A enabled but no endpoints found
    [    2.157416] Adding alias for supply vdd,iva_coproc -> vdd,4a0025cc.voltdm
    [    2.164436] vip1-s0: Port B enabled but no endpoints found
    [    2.169771] vip1-s1: Port B enabled but no endpoints found[    2.173442] Adding alias for supply vbb,iva_coproc -> vbb,4a0025cc.voltdm
    [    2.183483] coproc iva_coproc: coproc_probe result=0
    [    2.188506] coproc dsp_coproc: probe
    [    2.192182] Adding alias for supply vdd,dsp_coproc -> vdd,4a0025e0.voltdm
    [    2.199054] Adding alias for supply vbb,dsp_coproc -> vbb,4a0025e0.voltdm
    [    2.207001] coproc dsp_coproc: coproc_probe result=0
    [    2.216304] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
    [    2.267520] ledtrig-cpu: registered to indicate activity on CPUs
    [    2.273879] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
    [    2.295949] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
    [    2.302223] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
    [    2.308590] alg: skcipher: setkey failed on test 5 for ecb-des-omap: flags=100
    [    2.313558] mmc0: host does not support reading read-only switch. assuming write-enable.
    [    2.313624] mmc0: new SDHC card at address 0001
    [    2.314148] mmcblk0: mmc0:0001 SD4GB 3.64 GiB
    [    2.333056] ata1: SATA link down (SStatus 0 SControl 300)
    [    2.334166]  mmcblk0: p1 p2
    [    2.341728] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    2.349848] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    2.362739] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
    [    2.388513] usbcore: registered new interface driver usbhid
    [    2.394152] usbhid: USB HID core driver
    [    2.399095]  remoteproc0: 58820000.ipu is available
    [    2.404070]  remoteproc0: Note: remoteproc is still under development and considered experimental.
    [    2.413068]  remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    2.423601]  remoteproc0: Direct firmware load failed with error -2
    [    2.429895]  remoteproc0: Falling back to user helper
    [    2.435108]  remoteproc1: 55020000.ipu is available
    [    2.440008]  remoteproc1: Note: remoteproc is still under development and considered experimental.
    [    2.449190]  remoteproc1: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    2.459765]  remoteproc1: Direct firmware load failed with error -2
    [    2.466179]  remoteproc2: 40800000.dsp is available
    [    2.471078]  remoteproc2: Note: remoteproc is still under development and considered experimental.
    [    2.480102]  remoteproc1: Falling back to user helper
    [    2.485395]  remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    2.495939]  remoteproc2: Direct firmware load failed with error -2
    [    2.502233]  remoteproc2: Falling back to user helper
    [    2.507653]  remoteproc3: 41000000.dsp is available
    [    2.512553]  remoteproc3: Note: remoteproc is still under development and considered experimental.
    [    2.521584]  remoteproc3: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    2.532090]  remoteproc3: Direct firmware load failed with error -2
    [    2.538538]  remoteproc3: Falling back to user helper
    [    2.547522] [LOUIS sound/soc/codecs/bt-sco.c, bt_sco_probe, 56]
    [    2.554317] tlv320aic3x-codec 1-0018: Failed to get supply 'IOVDD': -517
    [    2.561049] tlv320aic3x-codec 1-0018: Failed to request supplies: -517
    [    2.567716] i2c 1-0018: Driver tlv320aic3x-codec requests probe deferral
    [    2.574650] tlv320aic3x-codec 1-0019: Failed to get supply 'IOVDD': -517
    [    2.581381] tlv320aic3x-codec 1-0019: Failed to request supplies: -517
    [    2.588038] i2c 1-0019: Driver tlv320aic3x-codec requests probe deferral
    [    2.594962] tlv320aic3x-codec 1-001a: Failed to get supply 'IOVDD': -517
    [    2.601691] tlv320aic3x-codec 1-001a: Failed to request supplies: -517
    [    2.608352] i2c 1-001a: Driver tlv320aic3x-codec requests probe deferral
    [    2.615579] platform primary_sound: Driver asoc-simple-card requests probe deferral
    [    2.624134] davinci-mcasp 48468000.mcasp: numevt will be ignored due to errata i868
    [    2.632456] davinci-mcasp 48474000.mcasp: DAI is shared
    [    2.637975] davinci-mcasp 48474000.mcasp: numevt will be ignored due to errata i868
    [    2.647412] oprofile: using timer interrupt.
    [    2.651768] nf_conntrack version 0.5.0 (7862 buckets, 31448 max)
    [    2.658248] ip_tables: (C) 2000-2006 Netfilter Core Team
    [    2.663674] TCP: cubic registered
    [    2.667002] Initializing XFRM netlink socket
    [    2.671306] NET: Registered protocol family 17
    [    2.675801] NET: Registered protocol family 15
    [    2.680333] Bridge firewalling registered
    [    2.684377] can: controller area network core (rev 20120528 abi 9)
    [    2.690650] NET: Registered protocol family 29
    [    2.695128] can: raw protocol (rev 20120528)
    [    2.699453] 8021q: 802.1Q VLAN Support v1.8
    [    2.703734] Key type dns_resolver registered
    [    2.708024] NET: Registered protocol family 41
    [    2.713162] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.voltdm
    [    2.719474] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.voltdm
    [    2.727486] Power Management for TI OMAP4+ devices.
    [    2.732536] ThumbEE CPU extension supported.
    [    2.736874] Registering SWP/SWPB emulation handler
    [    2.741682] SmartReflex Class3 initialized
    [    2.747374] vmmcwl_fixed: disabling
    [    2.750876] regulator-dummy: disabling
    [    2.754880] dmm 4e000000.dmm: workaround for errata i878 in use
    [    2.762570] dmm 4e000000.dmm: initialized all PAT entries
    [    2.769436] evm_3v3_sw: 3300 mV
    [    2.772709] evm_3v3_sw: supplied by sysen1
    [    2.777253] aic_dvdd: 1800 mV
    [    2.780352] aic_dvdd: supplied by evm_3v3_sw
    [    2.784888] vtt_fixed: 1350 mV
    [    2.788061] vtt_fixed: supplied by sysen2
    [    3.783383] omap_i2c 4807a000.i2c: controller timed out
    [    3.803399] pcf857x: probe of 3-0021 failed with error -110
    [    3.809055] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
    [    3.816538] [LOUIS sound/soc/soc-devres.c, devm_snd_soc_register_card, 112]
    [    3.823586] [LOUIS sound/soc/soc-core.c, snd_soc_register_card, 4163]
    [    3.830058] [LOUIS sound/soc/soc-core.c, snd_soc_instantiate_card, 1865]
    [    3.836800] [LOUIS sound/soc/soc-core.c, snd_soc_instantiate_card, 1873]
    [    3.843542] [LOUIS sound/soc/soc-core.c, snd_soc_instantiate_card, 1881]
    [    3.850272] [LOUIS sound/soc/soc-core.c, snd_soc_instantiate_card, 1891]
    [    3.857820] asoc-simple-card primary_sound:  bt-sco-pcm <-> 48468000.mcasp mapping ok
    [    3.865708] asoc-simple-card primary_sound: ASoC: no source widget found for HPLOUT
    [    3.873412] asoc-simple-card primary_sound: ASoC: Failed to add route HPLOUT -> direct -> Headphone Jack
    [    3.882934] asoc-simple-card primary_sound: ASoC: no source widget found for HPROUT
    [    3.890637] asoc-simple-card primary_sound: ASoC: Failed to add route HPROUT -> direct -> Headphone Jack
    [    3.900171] asoc-simple-card primary_sound: ASoC: no source widget found for LLOUT
    [    3.907786] asoc-simple-card primary_sound: ASoC: Failed to add route LLOUT -> direct -> Line Out
    [    3.916708] asoc-simple-card primary_sound: ASoC: no source widget found for RLOUT
    [    3.924322] asoc-simple-card primary_sound: ASoC: Failed to add route RLOUT -> direct -> Line Out
    [    3.933234] asoc-simple-card primary_sound: ASoC: no sink widget found for MIC3L
    [    3.940673] asoc-simple-card primary_sound: ASoC: Failed to add route Mic Jack -> direct -> MIC3L
    [    3.949595] asoc-simple-card primary_sound: ASoC: no sink widget found for MIC3R
    [    3.957063] asoc-simple-card primary_sound: ASoC: Failed to add route Mic Jack -> direct -> MIC3R
    [    3.965989] asoc-simple-card primary_sound: ASoC: no source widget found for Mic Bias
    [    3.973864] asoc-simple-card primary_sound: ASoC: Failed to add route Mic Bias -> direct -> Mic Jack
    [    3.983036] asoc-simple-card primary_sound: ASoC: no sink widget found for LINE1L
    [    3.990607] asoc-simple-card primary_sound: ASoC: Failed to add route Line In -> direct -> LINE1L
    [    3.999533] asoc-simple-card primary_sound: ASoC: no sink widget found for LINE1R
    [    4.007067] asoc-simple-card primary_sound: ASoC: Failed to add route Line In -> direct -> LINE1R
    [    4.063367] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
    [    4.069484] davinci_mdio 48485000.mdio: detected phy mask fffffff8
    [    4.081884] libphy: 48485000.mdio: probed
    [    4.085921] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver unknown
    [    4.093965] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver unknown
    [    4.102441] cpsw 48484000.ethernet: Detected MACID = 7c:ec:79:9c:14:5a
    [    4.109680] cpsw 48484000.ethernet: cpsw: Detected MACID = a0:f6:fd:c2:26:7d
    [    4.117619] omap_rtc 48838000.rtcss: setting system clock to 2000-01-01 00:00:01 UTC (946684801)
    [    4.126465] sr_init: No PMIC hook to init smartreflex
    [    4.131747] sr_init: platform driver register failed for SR
    [    4.146181] ALSA device list:
    [    4.149162]   #0: DRA7xx-EVM
    [    4.420956] EXT4-fs (mmcblk0p2): recovery complete
    [    4.432093] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    [    4.440269] VFS: Mounted root (ext4 filesystem) on device 179:2.
    [    4.447869] devtmpfs: mounted
    [    4.451087] Freeing unused kernel memory: 376K (c0923000 - c0981000)
    INIT: version 2.88 booting
    Starting udev
    [    5.126872] udevd[1161]: starting version 182
    [    5.479680]  remoteproc3: failed to load dra7-dsp2-fw.xe66
    [    5.583695]  remoteproc2: powering up 40800000.dsp
    [    5.588517]  remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 929770
    [    5.614828] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
    [    5.620720] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
    [    5.626649] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
    udevd[1317]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory
    
    [    5.730213]  remoteproc0: failed to load dra7-ipu1-fw.xem4
    udevd[1328]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory
    
    [    5.810544]  remoteproc2: remote processor 40800000.dsp is now up
    [    5.840346] virtio_rpmsg_bus virtio0: rpmsg host is online
    [    5.859215]  remoteproc2: registered virtio0 (type 7)
    [    5.860413] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x36
    [    5.860544] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x37
    [    5.860639] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x3b
    [    5.860758] rpmsg_rpc rpmsg2: probing service rpmsg-dce-dsp with src 1024 dst 59
    [    5.861688] rpmsg_rpc rpmsg2: published functions = 8
    [    6.556475]  remoteproc1: powering up 55020000.ipu
    [    6.561294]  remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 3484972
    [    6.574905] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
    [    6.644057]  remoteproc1: remote processor 55020000.ipu is now up
    [    6.650805] virtio_rpmsg_bus virtio1: rpmsg host is online
    [    6.656465]  remoteproc1: registered virtio1 (type 7)
    [    6.662077] virtio_rpmsg_bus virtio1: creating channel rpmsg-rpc addr 0x3b
    [    6.670073] rpmsg_rpc rpmsg3: probing service rpmsg-dce with src 1024 dst 59
    [    6.680764] rpmsg_rpc rpmsg3: published functions = 8
    [    7.238971] dwc3 48890000.usb: otg: primary host xhci-hcd.0.auto registered
    [    7.246029] dwc3 48890000.usb: otg: shared host xhci-hcd.0.auto registered
    [    7.252935] dwc3 48890000.usb: otg: can't start till gadget registers
    [    7.259573] dwc3 488d0000.usb: otg: primary host xhci-hcd.1.auto registered
    [    7.266835] dwc3 488d0000.usb: otg: shared host xhci-hcd.1.auto registered
    [    7.273753] dwc3 488d0000.usb: otg: can't start till gadget registers
    [    7.394349] Number of LUNs=8
    [    7.397254] Mass Storage Function, version: 2009/09/11
    [    7.402416] LUN: removable file: (no medium)
    [    7.406763] Number of LUNs=1
    [    7.409756] LUN: file: /dev/ram0
    [    7.412996] Number of LUNs=1
    [    7.416069] g_mass_storage gadget: Mass Storage Gadget, version: 2009/09/11
    [    7.423058] g_mass_storage gadget: userspace failed to provide iSerialNumber
    [    7.430165] g_mass_storage gadget: g_mass_storage ready
    [    7.435430] dwc3 48890000.usb: otg: gadget gadget registered
    [    7.441148] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
    [    7.447809] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
    [    7.456076] xhci-hcd xhci-hcd.0.auto: irq 427, io mem 0x48890000
    [    7.464349] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
    [    7.471178] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    [    7.478496] usb usb1: Product: xHCI Host Controller
    [    7.483443] usb usb1: Manufacturer: Linux 3.14.49 xhci-hcd
    [    7.488956] usb usb1: SerialNumber: xhci-hcd.0.auto
    [    7.498447] hub 1-0:1.0: USB hub found
    [    7.502259] hub 1-0:1.0: 1 port detected
    [    7.511009] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
    [    7.518003] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
    [    7.526278] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
    [    7.533099] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    [    7.540503] usb usb2: Product: xHCI Host Controller
    [    7.545440] usb usb2: Manufacturer: Linux 3.14.49 xhci-hcd
    [    7.550951] usb usb2: SerialNumber: xhci-hcd.0.auto
    [    7.556475] hub 2-0:1.0: USB hub found
    [    7.560280] hub 2-0:1.0: 1 port detected
    [    7.685669] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
    Starting Bootlog daemon: bootlogd: cannot allocate pseudo tty: No such file or directory
    bootlogd.
    rm: can't stat '/var/lib/urandom/random-seed': Not a directory
    urandom start: failed.
    [    7.969323] random: nonblocking pool is initialized
    ALSA: Restoring mixer settings...
    Thu Sep  3 18:41:00 UTC 2015
    INIT: Entering runlevel: 5
    Configuring network interfaces... [    8.652991] net eth0: initializing cpsw version 1.15 (0)
    [    8.737448] net eth0: phy found : id is : 0x1410dd1
    [    8.747475] 8021q: adding VLAN 0 to HW filter on device eth0
    done.
    mkdir: can't create directory '/var/lib/': Not a directory
    chown: /var/lib/dbus: Not a directory
    chgrp: /var/lib/dbus: Not a directory
    Failed to open "/etc/machine-id": No such file or directory
    Starting system message bus: dbus.
    UIM SYSFS Node Not Found
    Starting telnet daemon.
    Starting tiipclad daemon
    GateMP support enabled on host
    
    Opened log file: lad.txt
    
    numProcessors = 5 id = 0 baseId = 0
    
    Spawned daemon: /usr/bin/lad_dra7xx
    
    .
    Starting rpcbind daemon...rpcbind: cannot create socket for udp6
    rpcbind: cannot create socket for tcp6
    done.
    creating NFS state directory: mkdir: can't create directory '/var/lib/': Not a directory
    /etc/rc5.d/S19nfscommon: line 35: cd: /var/lib/nfs: Not a directory
    chown: /var/lib/nfs: Not a directory
    done
    starting statd: done
    NFS daemon support not enabled in kernel
    Starting syslogd/klogd: done
    Starting thttpd.
    [    9.556127] net eth1: initializing cpsw version 1.15 (0)
    [    9.647450] net eth1: phy found : id is : 0x1410dd1
    [    9.656519] 8021q: adding VLAN 0 to HW filter on device eth1
    [    9.670996] device eth0 entered promiscuous mode
    [    9.679799] device eth1 entered promiscuous mode
    [    9.687455] br0: port 2(eth1) entered forwarding state
    [    9.692627] br0: port 2(eth1) entered forwarding state
    Enabling thermal zones...
    *** Running User Application ***
    Packet dump deactivate
    Stopping Bootlog daemon:
    
    
    2017.06.13 11:00 AM
    
    
    This version is for J6
    
    
    [    9.743473] br0: port 2(eth1) entered disabled state
    bootlogd.
    
    [CB_Server_Client.c, main, 837] uart_OpenComport configuration: cport_nr (0), bdrate (115200), mode (8), mode (N), mode (1), mode ()
    [uart.c, uart_OpenComport, 151] uart_OpenComport configuration: Cport[comport_number] (3)
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    root@wnc-cb:~# [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [   12.739377] libphy: 48485000.mdio:01 - Link is Up - 1000/Full
    [   12.745524] br0: port 1(eth0) entered forwarding state
    [   12.750703] br0: port 1(eth0) entered forwarding state
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [   17.106954] omap_hwmod: mmu_ipu2: _wait_target_disable failed
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 1
     ______
    [CB_Server_Client.c, sync_AB_status, 424] ______ CB GPIO 146 1, can go ______
    [CB_Server_Client.c, send_CB_hardware_ver_to_AB, 559] write CB hardware verison total (4) Bytes, hw: (0110)
    CB_Server_Client: CB hardware version 0110
    
    
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 1
     ______
    [CB_Server_Client.c, sync_AB_status, 429] ______ CB GPIO 146 LOW, AB booting ______
    [CB_Server_Client.c, sync_AB_status, 420] ______ CB GPIO 146 status: 0
     ______
    [CB_Server_Client.c, sync_AB_status, 424] ______ CB GPIO 146 0, can go ______
    [CB_Server_Client.c, get_AB_model, 720] Wait for AB send model info
    
    
    [CB_Server_Client.c, get_AB_model, 724] Read AB model info (6) Bytes
    
    
    _AB_model[0]: 44
    _AB_model[1]: 52
    _AB_model[2]: 41
    _AB_model[3]: 37
    _AB_model[4]: 32
    _AB_model[5]: 58
    _AB_model[6]: 0
    _AB_model[7]: 0
    _AB_model[8]: 0
    _AB_model[9]: 0
    _AB_model[10]: 0
    _AB_model[11]: 0
    _AB_model[12]: 0
    _AB_model[13]: 0
    _AB_model[14]: 0
    _AB_model[15]: 0
    [CB_Server_Client.c, get_AB_model_info_finish, 759] CB get AB model info finish, gpio pull high
    [CB_Server_Client.c, main, 896] ulpi on/off : ULPI turn off (J6 eco)
    [   27.763359] br0: port 1(eth0) entered forwarding state
    
    

    BRs

    Louis

  • Louis,

    Version 3.00.00.03 -> Kernel 4.4 -> Requires the mono patch

    Version 7.02.00.02 -> Kernel 3.14 -> Mono patch not required

    Does "aplay/arecord -c 1 -r48000 -fS16_LE ..." work in GLSDK 7.02.00.02 with the dummy codec? It should. If it doesn't we need to make sure that the BCLK required for those parameters can actually be generated with your current clock settings.

    Please also check if there are more logs in /proc/kmsg.

  • Hi Misael,

    1. I want to solve issue in 3.00.00.03 first.

    2. After modifying DTS, it still has clock frequency issue in 3.00.00.03, the following is log.

    ---------------------- LOG -----------------------

    root@wnc-j6:~# aplay -D hw:0 i2s_1k_tone_16_bits_8k_sample_rate.wav
    Playing WAVE 'i2s_1k_tone_16_bits_8k_sample_rate.wav' : Signed 16 bit Little Endian, Rate 8000 Hz, Mono
    [ 433.049650] davinci-mcasp 48468000.mcasp: Too fast reference clock (265920000)
    [ 433.057076] davinci-mcasp 48468000.mcasp: Sample-rate is off by -241 PPM
    root@wnc-j6:~#

    3. I append the DTS file what I used

    ---------------------- DTS -----------------------

    4530.dra72-evm-common.dtsi.txt
    /*
     * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    /dts-v1/;
    
    #include "dra72x.dtsi"
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clk/ti-dra7-atl.h>
    
    / {
    	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
    
    	aliases {
    		display0 = &hdmi0;
    		display1 = &lcd2;
    		sound0 = &snd0;
    		sound1 = &hdmi;
    	};
    
    	evm_3v3_sw: fixedregulator-evm_3v3 {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	aic_dvdd: fixedregulator-aic_dvdd {
    		/* TPS77018DBVT */
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd";
    		vin-supply = <&evm_3v3_sw>;
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    	};
    
    	evm_3v3_sd: fixedregulator-sd {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sd";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    		enable-active-high;
    	};
    
    #if 0
    	extcon_usb1: extcon_usb1 {
    		compatible = "linux,extcon-usb-gpio";
    		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
    	};
    
    	extcon_usb2: extcon_usb2 {
    		compatible = "linux,extcon-usb-gpio";
    		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
    	};
    #endif
    
    	hdmi0: connector {
    		compatible = "hdmi-connector";
    		status = "disabled";
    		label = "hdmi";
    
    		type = "a";
    
    		port {
    			hdmi_connector_in: endpoint {
    				remote-endpoint = <&tpd12s015_out>;
    			};
    		};
    	};
    
    	tpd12s015: encoder {
    		compatible = "ti,tpd12s015";
    		status = "disabled";
    
    		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
    			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
    			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
    
    		ports {
    			#address-cells = <1>;
    			#size-cells = <0>;
    
    			port@0 {
    				reg = <0>;
    
    				tpd12s015_in: endpoint {
    					remote-endpoint = <&hdmi_out>;
    				};
    			};
    
    			port@1 {
    				reg = <1>;
    
    				tpd12s015_out: endpoint {
    					remote-endpoint = <&hdmi_connector_in>;
    				};
    			};
    		};
    	};
    
    	btsco: btsco@0 {
    		#sound-dai-cells = <0>;
    		compatible = "delta,dfbmcs320";
    		status = "okay";
    	};
    
    	snd0: sound@0 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "DRA7xx-EVM";
    #if 0
    		/* we do not have codec */
    		simple-audio-card,mclk-fs = <256>;
    #endif
    		simple-audio-card,widgets =
    			"Headphone", "Headphone Jack",
    			"Line", "Line Out",
    			"Microphone", "Mic Jack",
    			"Line", "Line In";
    		simple-audio-card,routing =
    			"Headphone Jack",       "HPLOUT",
    			"Headphone Jack",       "HPROUT",
    			"Line Out",		"LLOUT",
    			"Line Out",		"RLOUT",
    			"MIC3L",		"Mic Jack",
    			"MIC3R",		"Mic Jack",
    			"Mic Jack",		"Mic Bias",
    			"LINE1L",               "Line In",
    			"LINE1R",               "Line In";
    		status = "okay";
    
    #if 1
    		simple-audio-card,dai-link@0 {
    			format = "i2s";
    			bitclock-master = <&sound0_master>;
    			frame-master = <&sound0_master>;
    			bitclock-inversion;
    
    			sound0_master: cpu {
    				sound-dai = <&mcasp3>;
    				clocks = <&atl_clkin2_ck>;
    			};
    
    			codec {
    				sound-dai = <&btsco>;
    			};
    		};
    #else
    		simple-audio-card,format = "i2s";
    		simple-audio-card,bitclock-master = <&sound0_master>;
    		simple-audio-card,frame-master = <&sound0_master>;
    		simple-audio-card,bitclock-inversion;
    
    		sound0_master: simple-audio-card,cpu {
    			sound-dai = <&mcasp3>;
    			system-clock-frequency = <11289600>;
    		};
    
    		simple-audio-card,codec {
    			sound-dai = <&btsco>;
    			clocks = <&atl_clkin2_ck>;
    		};
    #endif
    	};
    
    #if 0
    	// GPIO5_8 is used for TDM pin
    	vmmcwl_fixed: fixedregulator-mmcwl {
    		compatible = "regulator-fixed";
    		regulator-name = "vmmcwl_fixed";
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    		gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
    		enable-active-high;
    	};
    #endif
    };
    
    &dra7_pmx_core {
    	mcasp3_pins: mcasp3_pins {
    		/* master */
    		pinctrl-single,pins = <
    			0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* dedicate: B19_MCASP3_AXR0 */
    			0x330 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* dedicate: C17_MCASP3_AXR1 */
    			0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* dedicate: B18_MCASP3_ACLKX*/
    			0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* dedicate: F15_MCASP3_FSX */
    		>;
    	};
    
            tps65917_pins_default: tps65917_pins_default {
                    pinctrl-single,pins = <
                            0x424 (PIN_INPUT_PULLUP | MUX_MODE1)    /* wakeup3.sys_nirq1 */
                    >;   
            };
    
    	mmc1_pins_default: mmc1_pins_default {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc2_pins_default: mmc2_pins_default {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc4_pins_default: mmc4_pins_default {
    		pinctrl-single,pins = <
    			0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
    			0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
    			0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
    			0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
    			0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
    			0x3fC (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
    		>;
    	};
    
    	dcan1_pins_default: dcan1_pins_default {
    		pinctrl-single,pins = <
    			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
    			0x418   (PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
    		>;
    	};
    
    	dcan1_pins_sleep: dcan1_pins_sleep {
    		pinctrl-single,pins = <
    			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
    			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
    		>;
    	};
    
    #if 0
    	// GPIO5_8 function in TDM
    	wlan_pins: pinmux_wlan_pins {
    		pinctrl-single,pins = <
    			0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_ctsn.mmc4_clk */
    			0x3ec (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_rtsn.mmc4_cmd */
    			0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_rxd.mmc4_dat0 */
    			0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_txd.mmc4_dat1 */
    			0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_ctsn.mmc4_dat2 */
    			0x3fc (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_rtsn.mmc4_dat3 */
    			0x2cc (PIN_OUTPUT | MUX_MODE14)		/* mcasp1_axr6.gpio5_8 - WLAN_EN */
    		>;
    	};
    #endif
    
    	wlirq_pins: pinmux_wlirq_pins {
    		pinctrl-single,pins = <
    			0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
    		>;
    	};
    };
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	tps65917: tps65917@58 {
    		compatible = "ti,tps65917";
    		reg = <0x58>;
    
    #if 0
    		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
    #else
                    pinctrl-names = "default";
                    pinctrl-0 = <&tps65917_pins_default>;
                    interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
                                            &dra7_pmx_core 0x424>;
                    interrupt-parent = <&gic>;
    #endif
    		interrupt-controller;
    		#interrupt-cells = <2>;
    
    		ti,system-power-controller;
    
    		tps65917_pmic {
    			compatible = "ti,tps65917-pmic";
    
    			tps65917_regulators: regulators {
    				smps1_reg: smps1 {
    					/* VDD_MPU */
    					regulator-name = "smps1";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps2_reg: smps2 {
    					/* VDD_CORE */
    					regulator-name = "smps2";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1150000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps3_reg: smps3 {
    					/* VDD_GPU IVA DSPEVE */
    					regulator-name = "smps3";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps4_reg: smps4 {
    					/* VDDS1V8 */
    					regulator-name = "smps4";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps5_reg: smps5 {
    					/* VDD_DDR */
    					regulator-name = "smps5";
    					regulator-min-microvolt = <1350000>;
    					regulator-max-microvolt = <1350000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo1_reg: ldo1 {
    					/* LDO1_OUT --> SDIO  */
    					regulator-name = "ldo1";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-always-on;
    					regulator-boot-on;
    					regulator-allow-bypass;
    				};
    
    				ldo3_reg: ldo3 {
    					/* VDDA_1V8_PHY */
    					regulator-name = "ldo3";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo5_reg: ldo5 {
    					/* VDDA_1V8_PLL */
    					regulator-name = "ldo5";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo4_reg: ldo4 {
    					/* VDDA_3V_USB: VDDA_USBHS33 */
    					regulator-name = "ldo4";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    				};
    			};
    		};
    
    		tps65917_power_button {
    			compatible = "ti,palmas-pwrbutton";
    			interrupt-parent = <&tps65917>;
    			interrupts = <1 IRQ_TYPE_NONE>;
    			wakeup-source;
    			ti,palmas-long-press-seconds = <6>;
    		};
    	};
    
    	pcf_lcd: gpio@20 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x20>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	pcf_gpio_21: gpio@21 {
    		status = "disabled";
    		compatible = "ti,pcf8575";
    		reg = <0x21>;
    		lines-initial-states = <0x1408>;
    		gpio-controller;
    		#gpio-cells = <2>;
    
    		interrupt-controller;
    		#interrupt-cells = <2>;
    	};
    
    	tlv320aic3106: tlv320aic3106@19 {
    		#sound-dai-cells = <0>;
    		compatible = "ti,tlv320aic3106";
    		reg = <0x19>;
    		adc-settle-ms = <40>;
    		ai3x-micbias-vg = <1>;		/* 2.0V */
    		status = "okay";
    
    		/* Regulators */
    		AVDD-supply = <&evm_3v3_sw>;
    		IOVDD-supply = <&evm_3v3_sw>;
    		DRVDD-supply = <&evm_3v3_sw>;
    		DVDD-supply = <&aic_dvdd>;
    	};
    };
    
    i2c_p3_exp: &i2c5 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	pcf_hdmi: pcf8575@26 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x26>;
    		gpio-controller;
    		#gpio-cells = <2>;
    		/*
    		 * initial state is used here to keep the mdio interface
    		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
    		 * VIN2_S0 driven high otherwise Ethernet stops working
    		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
    		 */
    		lines-initial-states = <0x0f2b>;
    
    		p1 {
    			/* vin6_sel_s0: high: VIN6, low: audio */
    			gpio-hog;
    			gpios = <1 GPIO_ACTIVE_HIGH>;
    			output-low;
    			line-name = "vin6_sel_s0";
    		};
    	};
    };
    
    &mcspi1 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {    
        spi-max-frequency = <100000>;
        reg = <0>; 
            compatible = "rohm,dh2228fv";   
            status = "okay" ; 
            };   
            spidev@1
            {    
        spi-max-frequency = <100000>;
        reg = <1>; 
            compatible = "rohm,dh2228fv";
            status = "okay" ; 
            };     
            spidev@3
            {    
        spi-max-frequency = <100000>;
        reg = <3>; 
            compatible = "rohm,dh2228fv";   
            status = "okay" ; 
            };
    };
    
    &mcspi2 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {
        spi-max-frequency = <100000>;
        reg = <0>;
            compatible = "rohm,dh2228fv";
            };
    };
    
    &mcspi3 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {
        spi-max-frequency = <100000>;
        reg = <0>;
            compatible = "rohm,dh2228fv";
            };
    };
    
    &uart1 {
    	status = "okay";
    	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
    			      <&dra7_pmx_core 0x3e0>;
    };
    
    &uart3 {
    	status = "okay";
    };
    
    &elm {
    	status = "okay";
    };
    
    &gpmc {
    	/*
    	 * For the existing IOdelay configuration via U-Boot we don't
    	 * support NAND on dra72-evm. Keep it disabled. Enabling it
    	 * requires a different configuration by U-Boot.
    	 */
    	status = "disabled";
    	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
    	nand@0,0 {
    		/* To use NAND, DIP switch SW5 must be set like so:
    		 * SW5.1 (NAND_SELn) = ON (LOW)
    		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
    		 */
    		compatible = "ti,omap2-nand";
    		reg = <0 0 4>;          /* device IO registers */
    		interrupt-parent = <&gpmc>;
    		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
    			     <1 IRQ_TYPE_NONE>; /* termcount */
    		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */	/* device IO registers */
    		ti,nand-ecc-opt = "bch8";
    		ti,elm-id = <&elm>;
    		nand-bus-width = <16>;
    		gpmc,device-width = <2>;
    		gpmc,sync-clk-ps = <0>;
    		gpmc,cs-on-ns = <0>;
    		gpmc,cs-rd-off-ns = <80>;
    		gpmc,cs-wr-off-ns = <80>;
    		gpmc,adv-on-ns = <0>;
    		gpmc,adv-rd-off-ns = <60>;
    		gpmc,adv-wr-off-ns = <60>;
    		gpmc,we-on-ns = <10>;
    		gpmc,we-off-ns = <50>;
    		gpmc,oe-on-ns = <4>;
    		gpmc,oe-off-ns = <40>;
    		gpmc,access-ns = <40>;
    		gpmc,wr-access-ns = <80>;
    		gpmc,rd-cycle-ns = <80>;
    		gpmc,wr-cycle-ns = <80>;
    		gpmc,bus-turnaround-ns = <0>;
    		gpmc,cycle2cycle-delay-ns = <0>;
    		gpmc,clk-activation-ns = <0>;
    		gpmc,wait-monitoring-ns = <0>;
    		gpmc,wr-data-mux-bus-ns = <0>;
    		/* MTD partition table */
    		/* All SPL-* partitions are sized to minimal length
    		 * which can be independently programmable. For
    		 * NAND flash this is equal to size of erase-block */
    		#address-cells = <1>;
    		#size-cells = <1>;
    		partition@0 {
    			label = "NAND.SPL";
    			reg = <0x00000000 0x000020000>;
    		};
    		partition@1 {
    			label = "NAND.SPL.backup1";
    			reg = <0x00020000 0x00020000>;
    		};
    		partition@2 {
    			label = "NAND.SPL.backup2";
    			reg = <0x00040000 0x00020000>;
    		};
    		partition@3 {
    			label = "NAND.SPL.backup3";
    			reg = <0x00060000 0x00020000>;
    		};
    		partition@4 {
    			label = "NAND.u-boot-spl-os";
    			reg = <0x00080000 0x00040000>;
    		};
    		partition@5 {
    			label = "NAND.u-boot";
    			reg = <0x000c0000 0x00100000>;
    		};
    		partition@6 {
    			label = "NAND.u-boot-env";
    			reg = <0x001c0000 0x00020000>;
    		};
    		partition@7 {
    			label = "NAND.u-boot-env.backup1";
    			reg = <0x001e0000 0x00020000>;
    		};
    		partition@8 {
    			label = "NAND.kernel";
    			reg = <0x00200000 0x00800000>;
    		};
    		partition@9 {
    			label = "NAND.file-system";
    			reg = <0x00a00000 0x0f600000>;
    		};
    	};
    };
    
    &usb2_phy1 {
    	phy-supply = <&ldo4_reg>;
    };
    
    &usb2_phy2 {
    	phy-supply = <&ldo4_reg>;
    };
    
    &omap_dwc3_1 {
    //	extcon = <&extcon_usb1>;
    };
    
    &omap_dwc3_2 {
    //	extcon = <&extcon_usb2>;
    };
    
    &usb1 {
    	status = "ok";
    	dr_mode = "host";
    };
    
    &usb2 {
    	status = "ok";
    	dr_mode = "host";
    };
    
    &usb3 {
    	status = "disabled";
    };
    
    &mmc1 {
    	status = "okay";
    
    	vmmc-supply = <&evm_3v3_sw>;
    	vmmc_aux-supply = <&ldo1_reg>;
    	bus-width = <4>;
    	/*
    	 * SDCD signal is not being used here - using the fact that GPIO mode
    	 * is a viable alternative
    	 */
    	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
    	max-frequency = <192000000>;
    };
    
    &mmc2 {
    	/* SW5-3 in ON position */
    	status = "okay";
    
    	vmmc-supply = <&evm_3v3_sw>;
    	bus-width = <8>;
    	ti,non-removable;
    	max-frequency = <192000000>;
    };
    
    &mmc4 {
    #if 1
            status = "okay";
    
            bus-width = <4>; 
            pinctrl-names = "default";
            pinctrl-0 = <&mmc4_pins_default>;
    	vmmc-supply = <&evm_3v3_sw>;
    #else
    	status = "okay";
    	vmmc-supply = <&vmmcwl_fixed>;
    	bus-width = <4>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&wlan_pins &wlirq_pins>;
    	cap-power-off-card;
    	keep-power-in-suspend;
    	ti,non-removable;
    
    	#address-cells = <1>;
    	#size-cells = <0>;
    	wlcore: wlcore@0 {
    		compatible = "ti,wl1835";
    		reg = <2>;
    		interrupt-parent = <&gpio5>;
    		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    	};
    #endif
    };
    
    &mac {
    	status = "okay";
    };
    
    &dcan1 {
    	status = "ok";
    };
    
    &qspi {
    	status = "okay";
    
    	spi-max-frequency = <64000000>;
    	m25p80@0 {
    		compatible = "s25fl256s1";
    		spi-max-frequency = <64000000>;
    		reg = <0>;
    		spi-tx-bus-width = <1>;
    		spi-rx-bus-width = <4>;
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		/* MTD partition table.
    		 * The ROM checks the first four physical blocks
    		 * for a valid file to boot and the flash here is
    		 * 64KiB block size.
    		 */
    		partition@0 {
    			label = "QSPI.SPL";
    			reg = <0x00000000 0x000040000>;
    		};
    		partition@1 {
    			label = "QSPI.u-boot";
    			reg = <0x00040000 0x00100000>;
    		};
    		partition@2 {
    			label = "QSPI.u-boot-spl-os";
    			reg = <0x00140000 0x00080000>;
    		};
    		partition@3 {
    			label = "QSPI.u-boot-env";
    			reg = <0x001c0000 0x00010000>;
    		};
    		partition@4 {
    			label = "QSPI.u-boot-env.backup1";
    			reg = <0x001d0000 0x0010000>;
    		};
    		partition@5 {
    			label = "QSPI.kernel";
    			reg = <0x001e0000 0x0800000>;
    		};
    		partition@6 {
    			label = "QSPI.file-system";
    			reg = <0x009e0000 0x01620000>;
    		};
    	};
    };
    
    &hdmi {
    	status = "disabled";
    
    	port {
    		hdmi_out: endpoint {
    			remote-endpoint = <&tpd12s015_in>;
    		};
    	};
    };
    
    &atl {
    	assigned-clocks = <&abe_dpll_sys_clk_mux>,
    			  <&atl_gfclk_mux>,
    			  <&dpll_abe_ck>,
    			  <&dpll_abe_m2x2_ck>,
    			  <&atl_clkin1_ck>,
    			  <&atl_clkin2_ck>;
    	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
    	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
    			       <11289600>, <11289600>;
    
    	status = "disabled";
    
    	atl2 {
    		bws = <DRA7_ATL_WS_MCASP2_FSX>;
    		aws = <DRA7_ATL_WS_MCASP3_FSX>;
    	};
    };
    
    &mcasp3 {
    	#sound-dai-cells = <0>;
    #if 0 
    	fck_parent = "atl_clkin2_ck";
    #else
    	fck_parent = "atl_clkin1_ck";
    #endif
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcasp3_pins>;
    
    	status = "okay";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		1 2 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    &mailbox5 {
    	status = "okay";
    	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
    		status = "okay";
    	};
    	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
    		status = "okay";
    	};
    };
    
    &mailbox6 {
    	status = "okay";
    	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
    		status = "okay";
    	};
    };
    
    &mmu0_dsp1 {
    	status = "okay";
    };
    
    &mmu1_dsp1 {
    	status = "okay";
    };
    
    &mmu_ipu1 {
    	status = "okay";
    };
    
    &mmu_ipu2 {
    	status = "okay";
    };
    
    &ipu2 {
    	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
    	timers = <&timer3>;
    	watchdog-timers = <&timer4>, <&timer9>;
    };
    
    &ipu1 {
    	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
    	timers = <&timer11>;
    	watchdog-timers = <&timer7>, <&timer8>;
    };
    
    &dsp1 {
    	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
    	timers = <&timer5>;
    	watchdog-timers = <&timer10>;
    };
    
    &oppdm_mpu {
    	vdd-supply = <&smps1_reg>;
    };
    
    &oppdm_core {
    	vdd-supply = <&smps2_reg>;
    };
    
    &oppdm_dspeve {
    	vdd-supply = <&smps3_reg>;
    };
    
    &oppdm_gpu {
    	vdd-supply = <&smps3_reg>;
    };
    
    &oppdm_ivahd {
    	vdd-supply = <&smps3_reg>;
    };
    

    How should I modify clock to let it slowly?

    BRs

    Louis

  • I don't think it's possible to generate the exact BCLK rate needed for 8kHz, stereo, 16-bits/sample with your current DPLL_ABE settings. So, you need to lock the DPLL_ABE to a different frequency.

    The clock fed to McASP is provided by the ATL module, the frequency of that clock can be configured in the atl node in the device-tree file. This clock frequency also needs to be lowered.

    One possible setting can be as shown below.

    snd0 {

        ...

        sound0_master: simple-audio-card,cpu {
            sound-dai = <&mcasp3>;
            system-clock-frequency = <8192000>;
        };

    };

    ...

    &atl {
        assigned-clocks = <&abe_dpll_sys_clk_mux>,
                          <&atl_gfclk_mux>,
                          <&dpll_abe_ck>,
                          <&dpll_abe_m2x2_ck>,
                          <&atl_clkin1_ck>,
                          <&atl_clkin2_ck>;
        assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
        assigned-clock-rates = <0>, <0>, <122880000>, <245760000>,
                               <8192000>, <8192000>;

        ...

    };

  • Hi Misael,
    It cannot work after I modify DTS configuration...
    Kernel Panic...


    [ 7.235232] asoc-simple-card sound@0: New simple-card: DRA7xx-EVM
    [ 7.249052] asoc-simple-card sound@0: link 0:
    [ 7.455224] davinci-mcasp 48468000.mcasp: Update the bindings to use assigned-clocks!
    [ 7.464258] davinci-mcasp 48468000.mcasp: failed to reparent fck
    [ 8.618196] clock: dpll_abe_ck failed transition to 'locked'
    [ 9.773882] clock: dpll_abe_ck failed transition to 'locked'
    [ 9.781816] ------------[ cut here ]------------
    [ 9.786459] WARNING: CPU: 0 PID: 1 at drivers/clk/clk.c:680 clk_core_disable+0x60/0x68()
    [ 9.794581] Modules linked in:
    [ 9.797656] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 4.4.14 #33
    [ 9.804905] Hardware name: Generic DRA72X (Flattened Device Tree)
    [ 9.811020] Backtrace:
    [ 9.813493] [<c0012ba0>] (dump_backtrace) from [<c0012d3c>] (show_stack+0x18/0x1c)
    [ 9.821092] r6:c0b49e84 r5:00000000 r4:20000093 r3:00000000
    [ 9.826814] [<c0012d24>] (show_stack) from [<c02a5fac>] (dump_stack+0x88/0xa8)
    [ 9.834069] [<c02a5f24>] (dump_stack) from [<c00345f0>] (warn_slowpath_common+0x7c/0xb8)
    [ 9.842191] r5:000002a8 r4:00000000
    [ 9.845799] [<c0034574>] (warn_slowpath_common) from [<c0034650>] (warn_slowpath_null+0x24/0x2c)
    [ 9.854618] r8:00000004 r7:c0c326d8 r6:c0c32dc0 r5:80000093 r4:ef032080
    [ 9.861390] [<c003462c>] (warn_slowpath_null) from [<c057a5c8>] (clk_core_disable+0x60/0x68)
    [ 9.869867] [<c057a568>] (clk_core_disable) from [<c057a78c>] (clk_disable+0x2c/0x38)
    [ 9.877726] r4:ef152580 r3:00000000
    [ 9.881334] [<c057a760>] (clk_disable) from [<c0023b08>] (_disable_clocks+0x20/0x84)
    [ 9.889106] r5:fffffff0 r4:c0c32dc0

    BRs
    Louis
  • Louis,

    > [ 7.464258] davinci-mcasp 48468000.mcasp: failed to reparent fck

    This is caused by specified the functional clock by name instead of using a phandle. Please refer to the mcasp3 node in the dra7-evm.dts file as a reference on how to specify the functional clock parent.

    > [ 8.618196] clock: dpll_abe_ck failed transition to 'locked'

    The clock rates that I gave as an example worked fine in the J6 EVM. I tested that. What's the source clock being fed into the DPLL_ABE?

    You can try reverting the clock rate changes, boot the device and run "omapconf show dpll". We can tweak the clock rates once we know the other settings in your system and omapconf can provide the needed information.

  • Hi Misael,

    1. Audio interface with I2S driver finally can work well in GLSDK 3.00.00.03. Thanks for your support.

    2. Now I have to use aplay to playback a 1k tone with sample rate 8k, mono wav file in 7.02.00.02 but in vain (I use btsco codec).
    Everything seems good (without any error message) but I cannot get any signal from tx, rx by scope. (I do loopback test, that is, short AXR0 and AXR1)

    3. Could you please help this issue. Thank you very much.

    4. The attached file is my boot log and aplay log.      

    audio log.txt
    U-Boot SPL 2014.07 (Jun 14 2017 - 11:09:27)
    DRA752-GP ES1.1
    before do_io_settings
    before prcm_init
            |-before enable_basic_clocks
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
    Enable clock module - 4a008728
    Enable clock module - 4a008b30
    Enable clock module - 4a008b38
    Enable clock module - 4a008d20
    Enable clock module - 4ae07838
    Enable clock module - 4a009760
    Enable clock module - 4a009768
    Enable clock module - 4a009770
    Enable clock module - 4a009778
    Enable clock module - 4a009780
    Enable clock module - 4a009810
    Enable clock module - 4a009818
    Enable clock module - 4a008778
    Enable clock module - 4a008780
    Enable clock module - 4ae07840
    Enable clock module - 4a009328
    Enable clock module - 4a009330
    Enable clock module - 4a009738
    Enable clock module - 4ae07830
    Enable clock module - 4a009850
    Enable clock module - 4a0097a0
    Enable clock module - 4a0093d0
    Enable clock module - 4a009838
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
            |-before timer_init
            |-before scale_vcores
                    |-before vcores->core
    optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1030, using efuse value 970
                    |-before core
    do_scale_vcore: volt - 970 offset_code - 0x35
                    |-before recalibrate_iodelay
    KEEP 6_30(ETH_SEL) input
    switch to NVA_SDIO (6_29 input).....
    switch to HDMI_I2C_SEL (6_12 input).....
    Power off LGA Board....
                            |-before __recalibrate_iodelay
                                    |-before calibrate_iodelay
                                    |-before isolate_io
                                            |- isolate = 1
                                            |-  wait_on_value1CBBBBB�Kwait_on_value2
    IODELAY: IO delay recalibration successfully completed
                    |-before vcores->mpu
    optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=1090, using efuse value 1025
                    |-before mpu
    do_scale_vcore: volt - 1025 offset_code - 0x3b
                    |-before abb_setup
                    |-before mm
                    |-before mm
                    |-before gpu
    optimize_vcore_voltage:efuse 0x4a003b10 bits=16 Vnom=1250, using efuse value 1050
                    |-before gpu
    do_scale_vcore: volt - 1050 offset_code - 0x3d
                    |-before eve
    optimize_vcore_voltage:efuse 0x4a0025e0 bits=16 Vnom=1060, using efuse value 990
                    |-before eve
    do_scale_vcore: volt - 990 offset_code - 0x37
                    |-before iva
    optimize_vcore_voltage:efuse 0x4a0025cc bits=16 Vnom=1060, using efuse value 995
                    |-before iva
    do_scale_vcore: volt - 995 offset_code - 0x38
     |-before setup_dplls
    setup_dplls
    
     core Dpll locked, but not for ideal M = 277,N = 4 values, current values are M = 1330,N= 23
     before core[4a005120] Dpll wait_for_lock
    Core DPLL configured
    
     per Dpll locked, but not for ideal M = 20,N = 0 values, current values are M = 1280,N= ��j�I��KW$�Y?MX8140] Dpll wait_for_lock
    PER DPLL locked
    
     mpu Dpll locked, but not for ideal M = 625,N = 11 values, current values are M = 1470,N= 23
     before mpu[4a005160] Dpll wait_for_lock
    MPU DPLL locked
    
     before usb[4a008180] Dpll wait_for_lock
    
     before ddr[4a005210] Dpll wait_for_lock
    
     before gmac[4a0052a8] Dpll wait_for_lock
     |-before setup_warmreset_time
    before board_early_init_f
    before sdram_init
    >>sdram_init()
    in_sdram = 0
    >>do_sdram_init() 4c000000
    <<do_sdram_init() 4c000000
     size_prog = 20000000
    base=80000000 , maxsize=20000000 , cnt=8000000
    i=27
    get_ram_size() successful<<sdram_init()
    spl_mmc_load_image
    reading dra7-evm.dtb
    spl_load_image_fat_os: error reading image dra7-evm.dtb, err - -1
    reading u-boot.img
    reading u-boot.img
    before init_omap_revision
    before hw_data_init
    before watchdog_init
    before set_mux_conf_regs
    before prcm_init
    
    
    U-Boot 2014.07 (Jun 14 2017 - 11:09:27)
    
    CPU  : DRA752-GP ES1.1
    Board: DRA7xx
    I2C:   ready
    DRAM:  >>sdram_init()
    512 MiB
    NAND:  512 MiB
    MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
    *** Warning - bad CRC, using default environment
    
    serial# not set, setting...
    SATA link 0 timeout.
    AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
    flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
    scanning bus for devices...
    Found 0 device(s).
    SCSI:  Net:   Phy not found
    cpsw
    Hit any key to stop autoboot:  0
    Turn on SATA
    SATA SEL
    Turn on ULPI
    Turn on PCIE
    Keep ethernet down.....
    ==== This is old CB  =====
    switch to partitions #0, OK
    mmc0 is current device
    SD/MMC found on device 0
    reading uEnv.txt
    221 bytes read in 3 ms (71.3 KiB/s)
    Loaded environment from uEnv.txt
    Importing environment from mmc0 ...
    5123024 bytes read in 261 ms (18.7 MiB/s)
    101519 bytes read in 17 ms (5.7 MiB/s)
    Booting from mmc0 ...
    Kernel image @ 0x82000000 [ 0x000000 - 0x4e2bd0 ]
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffe4000, end 8ffffc8e ... OK
    
    Starting kernel ...
    
    
    Starting kernel 4
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 3.14.49 (root@louis-VirtualBox) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #63 SMP PREEMPT Wed Jun 14 11:27:22 CST 2017
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] Machine model: TI DRA742 Louis 20170724 12:00
    [    0.000000] Reserved memory: created CMA memory pool at 0x95800000, size 56 MiB
    [    0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 64 MiB
    [    0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9d000000, size 32 MiB
    [    0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9f000000, size 8 MiB
    [    0.000000] Reserved memory: initialized node dsp2_cma@9f000000, compatible id shared-dma-pool
    [    0.000000] cma: CMA: reserved 64 MiB at 91000000
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] DRA752 ES1.1
    [    0.000000] PERCPU: Embedded 8 pages/cpu @dfa49000 s8640 r8192 d15936 u32768
    [    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 128768
    [    0.000000] Kernel command line: console=ttyO2,115200n8 elevator=noop root=PARTUUID=9bebf980-02 rw rootwait earlyprintk fixrtc omapdrm.num_crtc=2 consoleblank=0 cma=64M rootfstype=ext4 snd.slots_reserved=1,1
    [    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
    [    0.000000] Memory: 273800K/519168K available (6675K kernel code, 689K rwdata, 2644K rodata, 376K init, 266K bss, 245368K reserved, 0K highmem)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    [    0.000000]     vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0xc0008000 - 0xc09220cc   (9321 kB)
    [    0.000000]       .init : 0xc0923000 - 0xc09811c0   ( 377 kB)
    [    0.000000]       .data : 0xc0982000 - 0xc0a2e520   ( 690 kB)
    [    0.000000]        .bss : 0xc0a2e52c - 0xc0a7103c   ( 267 kB)
    [    0.000000] Preemptible hierarchical RCU implementation.
    [    0.000000] NR_IRQS:16 nr_irqs:16 16
    [    0.000000] OMAP clockevent source: timer1 at 31475 Hz
    [    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns
    [    0.000030] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000396] Architected cp15 timer(s) running at 5.90MHz (virt).
    [    0.000432] sched_clock: 56 bits at 5MHz, resolution 169ns, wraps every 2911033065472ns
    [    0.000440] Switching to timer-based delay loop
    [    0.001455] Console: colour dummy device 80x30
    [    0.001474] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
    [    0.001481] This ensures that you still see kernel messages. Please
    [    0.001487] update your kernel commandline.
    [    0.001500] Calibrating delay loop (skipped), value calculated using timer frequency.. 11.80 BogoMIPS (lpj=59016)
    [    0.001514] pid_max: default: 32768 minimum: 301
    [    0.001623] Security Framework initialized
    [    0.001677] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.001688] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.025902] CPU: Testing write buffer coherency: ok
    [    0.026164] /cpus/cpu@0 missing clock-frequency property
    [    0.026200] /cpus/cpu@1 missing clock-frequency property
    [    0.026212] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.026239] Setting up static identity map for 0x8068a428 - 0x8068a498
    [    0.080822] CPU1: Booted secondary processor
    [    0.080850] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.080978] Brought up 2 CPUs
    [    0.080994] SMP: Total of 2 processors activated (23.60 BogoMIPS).
    [    0.081001] CPU: All CPU(s) started in SVC mode.
    [    0.081424] devtmpfs: initialized
    [    0.082159] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.083913] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.097603] omap_hwmod: tptc0 using broken dt data from edma-controller
    [    0.098109] omap_hwmod: tptc1 using broken dt data from edma-controller
    [    0.270441] pinctrl core: initialized pinctrl subsystem
    [    0.271224] regulator-dummy: no parameters
    [    0.275574] NET: Registered protocol family 16
    [    0.277452] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.279527] cpuidle: using governor ladder
    [    0.279537] cpuidle: using governor menu
    [    0.326421] syscon 4a002000.tisysconcore: regmap [mem 0x4a002000-0x4a0026cf] registered
    [    0.326755] syscon 4a002e00.tisyscon: regmap [mem 0x4a002e00-0x4a002e7b] registered
    [    0.329600] OMAP GPIO hardware version 0.1
    [    0.335970] irq: no irq domain found for /ocp/pinmux@4a003400 !
    [    0.343459] platform 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000
    [    0.343765] platform 55020000.ipu: assigned reserved memory node ipu2_cma@95800000
    [    0.344063] platform 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
    [    0.359456] platform 41000000.dsp: assigned reserved memory node dsp2_cma@9f000000
    [    0.363820] No ATAGs?
    [    0.363848] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
    [    0.363857] hw-breakpoint: maximum watchpoint size is 8 bytes.
    [    0.366791] OMAP DMA hardware revision 0.0
    [    0.394890] bio: create slab <bio-0> at 0
    [    0.410240] edma-dma-engine edma-dma-engine.0: TI EDMA DMA engine driver
    [    0.416414] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver
    [    0.417231] evm_3v3_sd: 3300 mV
    [    0.417547] evm_3v3_sw: 3300 mV
    [    0.417610] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to find supply vin
    [    0.417794] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to register regulator: -517
    [    0.417813] platform fixedregulator-evm_3v3_sw: Driver reg-fixed-voltage requests probe deferral
    [    0.418073] aic_dvdd: 1800 mV
    [    0.418135] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to find supply vin
    [    0.418319] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to register regulator: -517
    [    0.418337] platform fixedregulator-aic_dvdd: Driver reg-fixed-voltage requests probe deferral
    [    0.418594] vmmcwl_fixed: 1800 mV
    [    0.418914] vtt_fixed: 1350 mV
    [    0.418960] reg-fixed-voltage fixedregulator-vtt: Failed to find supply vin
    [    0.419137] reg-fixed-voltage fixedregulator-vtt: Failed to register regulator: -517
    [    0.419155] platform fixedregulator-vtt: Driver reg-fixed-voltage requests probe deferral
    [    0.422775] vgaarb: loaded
    [    0.423234] i2c-core: driver [palmas] using legacy suspend method
    [    0.423244] i2c-core: driver [palmas] using legacy resume method
    [    0.423840] SCSI subsystem initialized
    [    0.425098] usbcore: registered new interface driver usbfs
    [    0.425270] usbcore: registered new interface driver hub
    [    0.425454] usbcore: registered new device driver usb
    [    0.427789] palmas 0-0058: IRQ missing: skipping irq request
    [    0.428144] palmas 0-0058: Muxing GPIO a, PWM 0, LED 0
    [    0.428294] prom_parse: Bad cell count for /ocp/i2c@48070000/tps659038@58
    [    0.430467] smps12: 850 <--> 1250 mV at 1030 mV
    [    0.431985] smps3: 850 <--> 1250 mV at 1350 mV
    [    0.433675] smps45: 850 <--> 1150 mV at 990 mV
    [    0.435347] smps6: 850 <--> 1250 mV at 1050 mV
    [    0.436869] smps7: 850 <--> 1060 mV at 970 mV
    [    0.438537] smps8: 850 <--> 1250 mV at 1000 mV
    [    0.440037] smps9: 1800 mV
    [    0.442727] ldo1: 1800 <--> 3300 mV at 3000 mV
    [    0.451090] ldo2: 3300 mV
    [    0.461324] ldo3: 1800 mV
    [    0.462221] LDO4: no parameters
    [    0.462817] LDO5: no parameters
    [    0.463451] LDO6: no parameters
    [    0.464045] LDO7: no parameters
    [    0.464659] LDO8: no parameters
    [    0.471116] ldo9: 1050 mV
    [    0.481140] ldoln: 1800 mV
    [    0.491206] ldousb: 3300 mV
    [    0.492104] regen1: no parameters
    [    0.492690] regen2: no parameters
    [    0.493395] sysen1: no parameters
    [    0.493991] sysen2: no parameters
    [    0.494249] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
    [    0.495141] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
    [    0.495211] omap_i2c 4807a000.i2c: could not find pctldev for node /ocp/padconf@4844a000/pinmux_i2c4_pins, deferring probe
    [    0.495227] platform 4807a000.i2c: Driver omap_i2c requests probe deferral
    [    0.495649] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
    [    0.495936] media: Linux media interface: v0.10
    [    0.496087] Linux video capture interface: v2.00
    [    0.496316] pps_core: LinuxPPS API ver. 1 registered
    [    0.496325] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [    0.496440] PTP clock support registered
    [    0.497913] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
    [    0.498360] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
    [    0.499405] omap-iommu 40d01000.mmu: 40d01000.mmu registered
    [    0.499524] omap-iommu 40d02000.mmu: 40d02000.mmu registered
    [    0.499630] omap-iommu 58882000.mmu: 58882000.mmu registered
    [    0.499738] omap-iommu 55082000.mmu: 55082000.mmu registered
    [    0.499907] omap-iommu 41501000.mmu: 41501000.mmu registered
    [    0.500016] omap-iommu 41502000.mmu: 41502000.mmu registered
    [    0.500806] Advanced Linux Sound Architecture Driver Initialized.
    [    0.502198] Switched to clocksource arch_sys_counter
    [    0.520665] NET: Registered protocol family 2
    [    0.521365] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
    [    0.521404] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
    [    0.521474] TCP: Hash tables configured (established 4096 bind 4096)
    [    0.521511] TCP: reno registered
    [    0.521523] UDP hash table entries: 256 (order: 1, 8192 bytes)
    [    0.521543] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
    [    0.521727] NET: Registered protocol family 1
    [    0.521994] RPC: Registered named UNIX socket transport module.
    [    0.522004] RPC: Registered udp transport module.
    [    0.522011] RPC: Registered tcp transport module.
    [    0.522018] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [    0.523162] hw perfevents: enabled with ARMv7 Cortex-A15 PMU driver, 7 counters available
    [    0.526104] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.637300] VFS: Disk quotas dquot_6.5.2
    [    0.637413] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
    [    0.638008] NFS: Registering the id_resolver key type
    [    0.638043] Key type id_resolver registered
    [    0.638052] Key type id_legacy registered
    [    0.638083] jffs2: version 2.2. (NAND) (SUMMARY)  c 2001-2006 Red Hat, Inc.
    [    0.638272] msgmni has been set to 982
    [    0.642359] alg: No test for stdrng (krng)
    [    0.642560] NET: Registered protocol family 38
    [    0.642588] io scheduler noop registered (default)
    [    0.642597] io scheduler deadline registered
    [    0.642635] io scheduler cfq registered
    [    0.648796] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
    [    0.687107] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
    [    0.687122] pci_bus 0000:00: root bus resource [io  0x1000-0x10000]
    [    0.687134] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
    [    0.687146] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
    [    0.687669] PCI: bus0: Fast back to back transfers disabled
    [    0.687907] PCI: bus1: Fast back to back transfers enabled
    [    0.688027] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
    [    0.688044] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
    [    0.688057] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.688078] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.691911] pbias_mmc_omap5: 1800 <--> 3000 mV at 3000 mV
    [    0.692931] abb_mpu: 1100 <--> 1210 mV
    [    0.693299] abb_ivahd: 1060 <--> 1250 mV
    [    0.693655] abb_dspeve: 1060 <--> 1250 mV
    [    0.694010] abb_gpu: 1060 <--> 1280 mV
    [    0.695141] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
    [    0.699564] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 299, base_baud = 3000000) is a 8250
    [    0.700345] 4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 300, base_baud = 3000000) is a 8250
    [    0.701112] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 301, base_baud = 3000000) is a 8250
    [    1.850697] console [ttyS2] enabled
    [    1.855028] 48066000.serial: ttyS4 at MMIO 0x48066000 (irq = 302, base_baud = 3000000) is a 8250
    [    1.864650] 48420000.serial: ttyS6 at MMIO 0x48420000 (irq = 303, base_baud = 3000000) is a 8250
    [    1.875254] omap_rng 48090000.rng: OMAP Random Number Generator ver. 20
    [    1.882441] [drm] Initialized drm 1.1.0 20060810
    [    1.897712] brd: module loaded
    [    1.906357] loop: module loaded
    [    1.909834] (hci_tty): inside hci_tty_init
    [    1.914316] (hci_tty): allocated 249, 0
    [    1.920592] ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
    [    1.927361] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
    [    1.935942] ahci 4a140000.sata: flags: 64bit ncq sntf stag pm led clo only pmp pio slum part ccc apst
    [    1.946420] scsi0 : ahci_platform
    [    1.950223] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 336
    [    1.959513] mtdoops: mtd device (mtddev=name/number) must be supplied
    [    1.971326] usbcore: registered new interface driver asix
    [    1.976914] usbcore: registered new interface driver ax88179_178a
    [    1.983192] usbcore: registered new interface driver cdc_ether
    [    1.989210] usbcore: registered new interface driver smsc95xx
    [    1.995145] usbcore: registered new interface driver net1080
    [    2.000967] usbcore: registered new interface driver cdc_subset
    [    2.007067] usbcore: registered new interface driver zaurus
    [    2.012854] usbcore: registered new interface driver cdc_ncm
    [    2.018961] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    [    2.025534] ehci-pci: EHCI PCI platform driver
    [    2.030147] ehci-omap: OMAP-EHCI Host Controller driver
    [    2.035847] usbcore: registered new interface driver cdc_wdm
    [    2.041686] usbcore: registered new interface driver usb-storage
    [    2.048916] mousedev: PS/2 mouse device common for all mice
    [    2.056663] i2c-core: driver [rtc-ds1307] using legacy suspend method
    [    2.063149] i2c-core: driver [rtc-ds1307] using legacy resume method
    [    2.070210] omap_rtc 48838000.rtcss: rtc core: registered 48838000.rtcss as rtc0
    [    2.078518] i2c /dev entries driver
    [    2.302228] ata1: SATA link down (SStatus 0 SControl 300)
    [    3.082250] omap_i2c 48072000.i2c: controller timed out
    [    3.102228] tvp5158 1-0058: i2c i/o error: rc == -110 (should be 1)
    [    4.102222] omap_i2c 48072000.i2c: controller timed out
    [    4.122225] tvp5158 1-0058: i2c i/o error: rc == -110 (should be 1)
    [    4.128521] tvp5158 1-0058: ERROR: Chip id is not TVP5158
    [    4.134892] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
    [    4.141028] vip 48970000.vip: No explicit pinctrl resources data.
    [    4.148150] vip 48970000.vip: loading firmware vpdma-1b8.bin
    [    4.154127] vpe 489d0000.vpe: Device registered as /dev/video0
    [    4.160150] Driver for 1-wire Dallas network protocol.
    [    4.166415] coproc iva_coproc: probe
    [    4.170130] Adding alias for supply vdd,iva_coproc -> vdd,4a0025cc.voltdm
    [    4.176978] vip 48970000.vip: VPDMA firmware loaded
    [    4.181971] vip1-s1: Port A enabled but no endpoints found
    [    4.187326] Adding alias for supply vbb,iva_coproc -> vbb,4a0025cc.voltdm
    [    4.194349] vip1-s0: Port B enabled but no endpoints found
    [    4.199685] vip1-s1: Port B enabled but no endpoints found[    4.206614] coproc iva_coproc: coproc_probe result=0
    [    4.211638] coproc dsp_coproc: probe
    [    4.215323] Adding alias for supply vdd,dsp_coproc -> vdd,4a0025e0.voltdm
    [    4.222142] Adding alias for supply vbb,dsp_coproc -> vbb,4a0025e0.voltdm
    [    4.230420] coproc dsp_coproc: coproc_probe result=0
    [    4.239660] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
    [    4.283322] ledtrig-cpu: registered to indicate activity on CPUs
    [    4.289656] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
    [    4.311814] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
    [    4.318148] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
    [    4.324571] alg: skcipher: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.332261] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.340404] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.353372] mmc0: host does not support reading read-only switch. assuming write-enable.
    [    4.353706] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
    [    4.369376] mmc0: new high speed SDHC card at address 1234
    [    4.375727] mmcblk0: mmc0:1234 SA04G 3.70 GiB
    [    4.383250]  mmcblk0: p1 p2
    [    4.403312] usbcore: registered new interface driver usbhid
    [    4.408909] usbhid: USB HID core driver
    [    4.413885]  remoteproc0: 58820000.ipu is available
    [    4.418784]  remoteproc0: Note: remoteproc is still under development and considered experimental.
    [    4.427803]  remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.438314]  remoteproc0: Direct firmware load failed with error -2
    [    4.444741]  remoteproc1: 55020000.ipu is available
    [    4.449640]  remoteproc1: Note: remoteproc is still under development and considered experimental.
    [    4.458657]  remoteproc0: Falling back to user helper
    [    4.463890]  remoteproc1: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.474435]  remoteproc1: Direct firmware load failed with error -2
    [    4.480730]  remoteproc1: Falling back to user helper
    [    4.485924]  remoteproc2: 40800000.dsp is available
    [    4.490823]  remoteproc2: Note: remoteproc is still under development and considered experimental.
    [    4.500047]  remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.510636]  remoteproc2: Direct firmware load failed with error -2
    [    4.517188]  remoteproc3: 41000000.dsp is available
    [    4.522086]  remoteproc3: Note: remoteproc is still under development and considered experimental.
    [    4.531104]  remoteproc2: Falling back to user helper
    [    4.532241]  remoteproc3: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.532353]  remoteproc3: Direct firmware load failed with error -2
    [    4.532356]  remoteproc3: Falling back to user helper
    [    4.561350] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    4.569382] davinci-mcasp 48468000.mcasp: numevt will be ignored due to errata i868
    [    4.579211] oprofile: using timer interrupt.
    [    4.583581] nf_conntrack version 0.5.0 (7862 buckets, 31448 max)
    [    4.590032] ip_tables: (C) 2000-2006 Netfilter Core Team
    [    4.595460] TCP: cubic registered
    [    4.598789] Initializing XFRM netlink socket
    [    4.603103] NET: Registered protocol family 17
    [    4.607583] NET: Registered protocol family 15
    [    4.612114] Bridge firewalling registered
    [    4.616159] can: controller area network core (rev 20120528 abi 9)
    [    4.622440] NET: Registered protocol family 29
    [    4.626903] can: raw protocol (rev 20120528)
    [    4.631233] 8021q: 802.1Q VLAN Support v1.8
    [    4.635494] Key type dns_resolver registered
    [    4.639783] NET: Registered protocol family 41
    [    4.644951] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.voltdm
    [    4.651247] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.voltdm
    [    4.659289] Power Management for TI OMAP4+ devices.
    [    4.664356] ThumbEE CPU extension supported.
    [    4.668649] Registering SWP/SWPB emulation handler
    [    4.673466] SmartReflex Class3 initialized
    [    4.679088] vmmcwl_fixed: disabling
    [    4.682599] regulator-dummy: disabling
    [    4.686556] dmm 4e000000.dmm: workaround for errata i878 in use
    [    4.694256] dmm 4e000000.dmm: initialized all PAT entries
    [    4.701099] evm_3v3_sw: 3300 mV
    [    4.704384] evm_3v3_sw: supplied by sysen1
    [    4.708898] aic_dvdd: 1800 mV
    [    4.711993] aic_dvdd: supplied by evm_3v3_sw
    [    4.716557] vtt_fixed: 1350 mV
    [    4.719731] vtt_fixed: supplied by sysen2
    [    5.722230] omap_i2c 4807a000.i2c: controller timed out
    [    5.742245] pcf857x: probe of 3-0021 failed with error -110
    [    5.747906] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
    [    5.754838] asoc-simple-card sound@0:  bt-sco-pcm <-> 48468000.mcasp mapping ok
    [    5.762186] asoc-simple-card sound@0: ASoC: no source widget found for HPLOUT
    [    5.769412] asoc-simple-card sound@0: ASoC: Failed to add route HPLOUT -> direct -> Headphone Jack
    [    5.778427] asoc-simple-card sound@0: ASoC: no source widget found for HPROUT
    [    5.785607] asoc-simple-card sound@0: ASoC: Failed to add route HPROUT -> direct -> Headphone Jack
    [    5.794619] asoc-simple-card sound@0: ASoC: no source widget found for LLOUT
    [    5.801699] asoc-simple-card sound@0: ASoC: Failed to add route LLOUT -> direct -> Line Out
    [    5.810098] asoc-simple-card sound@0: ASoC: no source widget found for RLOUT
    [    5.817189] asoc-simple-card sound@0: ASoC: Failed to add route RLOUT -> direct -> Line Out
    [    5.825589] asoc-simple-card sound@0: ASoC: no sink widget found for MIC3L
    [    5.832506] asoc-simple-card sound@0: ASoC: Failed to add route Mic Jack -> direct -> MIC3L
    [    5.840894] asoc-simple-card sound@0: ASoC: no sink widget found for MIC3R
    [    5.847830] asoc-simple-card sound@0: ASoC: Failed to add route Mic Jack -> direct -> MIC3R
    [    5.856232] asoc-simple-card sound@0: ASoC: no source widget found for Mic Bias
    [    5.863586] asoc-simple-card sound@0: ASoC: Failed to add route Mic Bias -> direct -> Mic Jack
    [    5.872248] asoc-simple-card sound@0: ASoC: no sink widget found for LINE1L
    [    5.879240] asoc-simple-card sound@0: ASoC: Failed to add route Line In -> direct -> LINE1L
    [    5.887639] asoc-simple-card sound@0: ASoC: no sink widget found for LINE1R
    [    5.894643] asoc-simple-card sound@0: ASoC: Failed to add route Line In -> direct -> LINE1R
    [    5.952209] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
    [    5.958328] davinci_mdio 48485000.mdio: detected phy mask e7c0fffe
    [    5.983083] libphy: 48485000.mdio: probed
    [    5.987110] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver unknown
    [    5.995156] davinci_mdio 48485000.mdio: phy[16]: device 48485000.mdio:10, driver unknown
    [    6.003331] davinci_mdio 48485000.mdio: phy[17]: device 48485000.mdio:11, driver unknown
    [    6.011455] davinci_mdio 48485000.mdio: phy[18]: device 48485000.mdio:12, driver unknown
    [    6.019665] davinci_mdio 48485000.mdio: phy[19]: device 48485000.mdio:13, driver unknown
    [    6.027817] davinci_mdio 48485000.mdio: phy[20]: device 48485000.mdio:14, driver unknown
    [    6.035950] davinci_mdio 48485000.mdio: phy[21]: device 48485000.mdio:15, driver unknown
    [    6.044082] davinci_mdio 48485000.mdio: phy[27]: device 48485000.mdio:1b, driver unknown
    [    6.052685] cpsw 48484000.ethernet: Detected MACID = 7c:ec:79:9c:14:5a
    [    6.059917] cpsw 48484000.ethernet: cpsw: Detected MACID = d0:b5:c2:30:b7:c1
    [    6.067872] omap_rtc 48838000.rtcss: setting system clock to 2000-01-01 00:00:03 UTC (946684803)
    [    6.076704] sr_init: No PMIC hook to init smartreflex
    [    6.081988] sr_init: platform driver register failed for SR
    [    6.096491] ALSA device list:
    [    6.099472]   #0: DRA7xx-EVM
    [    7.019415] EXT4-fs (mmcblk0p2): recovery complete
    [    7.030468] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    [    7.038633] VFS: Mounted root (ext4 filesystem) on device 179:2.
    [    7.045821] devtmpfs: mounted
    [    7.049036] Freeing unused kernel memory: 376K (c0923000 - c0981000)
    INIT: version 2.88 booting
    Starting udev
    [    7.675070] udevd[1166]: starting version 182
    [    8.397945]  remoteproc3: failed to load dra7-dsp2-fw.xe66
    [    8.459009]  remoteproc0: failed to load dra7-ipu1-fw.xem4
    [    8.514310]  remoteproc2: powering up 40800000.dsp
    [    8.525658]  remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 929770
    [    8.541826] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
    [    8.547716] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
    [    8.553710] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
    [    8.658989]  remoteproc2: remote processor 40800000.dsp is now up
    [    8.666433] virtio_rpmsg_bus virtio0: rpmsg host is online
    [    8.672368]  remoteproc2: registered virtio0 (type 7)
    [    8.673120] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x36
    [    8.673257] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x37
    [    8.673360] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x3b
    [    8.673482] rpmsg_rpc rpmsg2: probing service rpmsg-dce-dsp with src 1024 dst 59
    [    8.707843] rpmsg_rpc rpmsg2: published functions = 8
    [    8.942892]  remoteproc1: powering up 55020000.ipu
    [    8.947717]  remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 3484972
    [    8.958027] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
    [    9.032599]  remoteproc1: remote processor 55020000.ipu is now up
    [    9.039274] virtio_rpmsg_bus virtio1: rpmsg host is online
    [    9.044840]  remoteproc1: registered virtio1 (type 7)
    [    9.047963] virtio_rpmsg_bus virtio1: creating channel rpmsg-rpc addr 0x3b
    [    9.048168] rpmsg_rpc rpmsg3: probing service rpmsg-dce with src 1024 dst 59
    [    9.064495] rpmsg_rpc rpmsg3: published functions = 8
    udevd[1417]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory
    
    udevd[1418]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory
    
    [    9.832159] dwc3 48890000.usb: otg: primary host xhci-hcd.0.auto registered
    [    9.839190] dwc3 48890000.usb: otg: shared host xhci-hcd.0.auto registered
    [    9.846108] dwc3 48890000.usb: otg: can't start till gadget registers
    [    9.852642] dwc3 488d0000.usb: otg: primary host xhci-hcd.1.auto registered
    [    9.859699] dwc3 488d0000.usb: otg: shared host xhci-hcd.1.auto registered
    [    9.867054] dwc3 488d0000.usb: otg: can't start till gadget registers
    [    9.954914] Number of LUNs=8
    [    9.957812] Mass Storage Function, version: 2009/09/11
    [    9.963001] LUN: removable file: (no medium)
    [    9.967294] Number of LUNs=1
    [    9.970254] LUN: file: /dev/ram0
    [    9.973505] Number of LUNs=1
    [    9.976498] g_mass_storage gadget: Mass Storage Gadget, version: 2009/09/11
    [    9.983507] g_mass_storage gadget: userspace failed to provide iSerialNumber
    [    9.990582] g_mass_storage gadget: g_mass_storage ready
    [    9.995836] dwc3 48890000.usb: otg: gadget gadget registered
    [   10.001545] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
    [   10.007776] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
    [   10.018195] xhci-hcd xhci-hcd.0.auto: irq 425, io mem 0x48890000
    [   10.024430] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
    [   10.031290] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    [   10.038573] usb usb1: Product: xHCI Host Controller
    [   10.043808] usb usb1: Manufacturer: Linux 3.14.49 xhci-hcd
    [   10.049330] usb usb1: SerialNumber: xhci-hcd.0.auto
    [   10.055858] hub 1-0:1.0: USB hub found
    [   10.059710] hub 1-0:1.0: 1 port detected
    [   10.063766] random: nonblocking pool is initialized
    [   10.071888] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
    [   10.079464] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
    [   10.091229] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
    [   10.099698] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    [   10.107087] usb usb2: Product: xHCI Host Controller
    [   10.112434] usb usb2: Manufacturer: Linux 3.14.49 xhci-hcd
    [   10.117947] usb usb2: SerialNumber: xhci-hcd.0.auto
    [   10.127189] hub 2-0:1.0: USB hub found
    [   10.131060] hub 2-0:1.0: 1 port detected
    [   10.574416] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
    Starting Bootlog daemon: bootlogd: cannot allocate pseudo tty: No such file or directory
    bootlogd.
    ALSA: Restoring mixer settings...
    No state is present for card DRA7xxEVM
    Found hardware: "DRA7xx-EVM" "" "" "" ""
    Hardware is initialized using a generic method
    No state is present for card DRA7xxEVM
    Thu Sep  3 18:41:00 UTC 2015
    INIT: Entering runlevel: 5
    Configuring network interfaces... [   11.481312] net eth0: initializing cpsw version 1.15 (0)
    [   11.566329] net eth0: phy found : id is : 0x1410dd1
    [   11.578208] 8021q: adding VLAN 0 to HW filter on device eth0
    done.
    Starting system message bus: dbus.
    UIM SYSFS Node Not Found
    Starting telnet daemon.
    Starting tiipclad daemon
    GateMP support enabled on host
    
    Opened log file: lad.txt
    
    numProcessors = 5 id = 0 baseId = 0
    
    Spawned daemon: /usr/bin/lad_dra7xx
    
    .
    Starting rpcbind daemon...rpcbind: cannot create socket for udp6
    rpcbind: cannot create socket for tcp6
    done.
    creating NFS state directory: done
    starting statd: done
    NFS daemon support not enabled in kernel
    Starting syslogd/klogd: done
    Starting thttpd.
    [   12.388796] net eth1: initializing cpsw version 1.15 (0)
    [   12.475289] net eth1: phy found : id is : 0xff001653
    [   12.484453] 8021q: adding VLAN 0 to HW filter on device eth1
    [   12.499039] device eth0 entered promiscuous mode
    [   12.507843] device eth1 entered promiscuous mode
    [   12.515527] br0: port 2(eth1) entered forwarding state
    [   12.520700] br0: port 2(eth1) entered forwarding state
    Enabling thermal zones...
    *** Running User Application ***
    Stopping Bootlog daemon: bootlogd.
    
    [   12.582292] br0: port 2(eth1) entered disabled state
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
     -vv wnc-cb:~# aplay -r8000 -D plughw:0,0 i2s_1k_tone_16_bits_8k_sample_rate.wav
    Playing WAVE 'i2s_1k_tone_16_bits_8k_sample_rate.wav' : Signed 16 bit Little Endian, Rate 8000 Hz, Mono
    Plug PCM: Hardware PCM card 0 'DRA7xx-EVM' device 0 subdevice 0
    Its setup is:
      stream       : PLAYBACK
      access       : RW_INTERLEAVED
      format       : S16_LE
      subformat    : STD
      channels     : 1
      rate         : 8000
      exact rate   : 8000 (8000/1)
      msbits       : 16
      buffer_size  : 4000
      period_size  : 1000
      period_time  : 125000
      tstamp_mode  : NONE
      period_step  : 1
      avail_min    : 1000
      period_event : 0
      start_threshold  : 4000
      stop_threshold   : 4000
      silence_threshold: 0
      silence_size : 0
      boundary     : 2097152000
      appl_ptr     : 0
      hw_ptr       : 0
    ##################################################+| 99%
    root@wnc-cb:~#
    

  • Is the loopback you mentioned in point (2) an external loopback (i.e. wiring AXR0 and AXR1 pins)?

    Could you run "omapconf show mcasp3" while aplay is running in the background?

    Please also double check that the McASP3 related pinmux setting is correct at the time aplay is running. Depending on your device-tree parameters, it's possible to have active and sleep pinctrl states. I believe you're defining only the active (default) state, so it should be good but let's double check.

    Also, please the check that the appl_ptr and hw_ptr are moving (cat /proc/asound/card0/pcm0p/sub0/status).
  • Hi Misael,

    1. I short AXR0 (pin define as Rx) and AXR1 (pin define as Tx), and the attached file is my log (including "omapconf show mcasp3" and cat card status...)

    4555.TI_debug_cb_failed.txt
    U-Boot SPL 2014.07 (Jun 14 2017 - 11:09:27)
    DRA752-GP ES1.1
    before do_io_settings
    before prcm_init
            |-before enable_basic_clocks
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
    Enable clock module - 4a008728
    Enable clock module - 4a008b30
    Enable clock module - 4a008b38
    Enable clock module - 4a008d20
    Enable clock module - 4ae07838
    Enable clock module - 4a009760
    Enable clock module - 4a009768
    Enable clock module - 4a009770
    Enable clock module - 4a009778
    Enable clock module - 4a009780
    Enable clock module - 4a009810
    Enable clock module - 4a009818
    Enable clock module - 4a008778
    Enable clock module - 4a008780
    Enable clock module - 4ae07840
    Enable clock module - 4a009328
    Enable clock module - 4a009330
    Enable clock module - 4a009738
    Enable clock module - 4ae07830
    Enable clock module - 4a009850
    Enable clock module - 4a0097a0
    Enable clock module - 4a0093d0
    Enable clock module - 4a009838
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
            |-before timer_init
            |-before scale_vcores
                    |-before vcores->core
    optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1030, using efuse value 970
                    |-before core
    do_scale_vcore: volt - 970 offset_code - 0x35
                    |-before recalibrate_iodelay
    KEEP 6_30(ETH_SEL) input
    switch to NVA_SDIO (6_29 input).....
    switch to HDMI_I2C_SEL (6_12 input).....
    Power off LGA Board....
                            |-before __recalibrate_iodelay
                                    |-before calibrate_iodelay
                                    |-before isolate_io
                                            |- isolate = 1
                                            |-  wait_on_value1CBBBBB�Kwait_on_value2
    IODELAY: IO delay recalibration successfully completed
                    |-before vcores->mpu
    optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=1090, using efuse value 1025
                    |-before mpu
    do_scale_vcore: volt - 1025 offset_code - 0x3b
                    |-before abb_setup
                    |-before mm
                    |-before mm
                    |-before gpu
    optimize_vcore_voltage:efuse 0x4a003b10 bits=16 Vnom=1250, using efuse value 1050
                    |-before gpu
    do_scale_vcore: volt - 1050 offset_code - 0x3d
                    |-before eve
    optimize_vcore_voltage:efuse 0x4a0025e0 bits=16 Vnom=1060, using efuse value 990
                    |-before eve
    do_scale_vcore: volt - 990 offset_code - 0x37
                    |-before iva
    optimize_vcore_voltage:efuse 0x4a0025cc bits=16 Vnom=1060, using efuse value 995
                    |-before iva
    do_scale_vcore: volt - 995 offset_code - 0x38
     |-before setup_dplls
    setup_dplls
    
     core Dpll locked, but not for ideal M = 277,N = 4 values, current values are M = 1330,N= 23
     before core[4a005120] Dpll wait_for_lock
    Core DPLL configured
    
     per Dpll locked, but not for ideal M = 20,N = 0 values, current values are M = 1280,N= ��jR���m?
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                                                                          W?S,&LML] Dpll wait_for_lock
    MPU DPLL locked
    
     before usb[4a008180] Dpll wait_for_lock
    
     before ddr[4a005210] Dpll wait_for_lock
    
     before gmac[4a0052a8] Dpll wait_for_lock
     |-before setup_warmreset_time
    before board_early_init_f
    before sdram_init
    >>sdram_init()
    in_sdram = 0
    >>do_sdram_init() 4c000000
    <<do_sdram_init() 4c000000
     size_prog = 20000000
    base=80000000 , maxsize=20000000 , cnt=8000000
    i=27
    get_ram_size() successful<<sdram_init()
    spl_mmc_load_image
    reading dra7-evm.dtb
    spl_load_image_fat_os: error reading image dra7-evm.dtb, err - -1
    reading u-boot.img
    reading u-boot.img
    before init_omap_revision
    before hw_data_init
    before watchdog_init
    before set_mux_conf_regs
    before prcm_init
    
    
    U-Boot 2014.07 (Jun 14 2017 - 11:09:27)
    
    CPU  : DRA752-GP ES1.1
    Board: DRA7xx
    I2C:   ready
    DRAM:  >>sdram_init()
    512 MiB
    NAND:  512 MiB
    MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
    *** Warning - bad CRC, using default environment
    
    serial# not set, setting...
    SATA link 0 timeout.
    AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
    flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
    scanning bus for devices...
    Found 0 device(s).
    SCSI:  Net:   Phy not found
    cpsw
    Hit any key to stop autoboot:  0
    Turn on SATA
    SATA SEL
    Turn on ULPI
    Turn on PCIE
    Keep ethernet down.....
    ==== This is old CB  =====
    switch to partitions #0, OK
    mmc0 is current device
    SD/MMC found on device 0
    reading uEnv.txt
    221 bytes read in 3 ms (71.3 KiB/s)
    Loaded environment from uEnv.txt
    Importing environment from mmc0 ...
    5124816 bytes read in 260 ms (18.8 MiB/s)
    101535 bytes read in 18 ms (5.4 MiB/s)
    Booting from mmc0 ...
    Kernel image @ 0x82000000 [ 0x000000 - 0x4e32d0 ]
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffe4000, end 8ffffc9e ... OK
    
    Starting kernel ...
    
    
    Starting kernel 4
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 3.14.49 (root@louis-VirtualBox) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #74 SMP PREEMPT Tue Jul 25 17:11:36 CST 2017
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] Machine model: TI DRA742 Louis 20170725 10:00
    [    0.000000] Reserved memory: created CMA memory pool at 0x95800000, size 56 MiB
    [    0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 64 MiB
    [    0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9d000000, size 32 MiB
    [    0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9f000000, size 8 MiB
    [    0.000000] Reserved memory: initialized node dsp2_cma@9f000000, compatible id shared-dma-pool
    [    0.000000] cma: CMA: reserved 64 MiB at 91000000
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] DRA752 ES1.1
    [    0.000000] PERCPU: Embedded 8 pages/cpu @dfa49000 s8640 r8192 d15936 u32768
    [    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 128768
    [    0.000000] Kernel command line: console=ttyO2,115200n8 elevator=noop root=PARTUUID=9bebf980-02 rw rootwait earlyprintk fixrtc omapdrm.num_crtc=2 consoleblank=0 cma=64M rootfstype=ext4 snd.slots_reserved=1,1
    [    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
    [    0.000000] Memory: 273800K/519168K available (6675K kernel code, 689K rwdata, 2644K rodata, 376K init, 266K bss, 245368K reserved, 0K highmem)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    [    0.000000]     vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0xc0008000 - 0xc09220cc   (9321 kB)
    [    0.000000]       .init : 0xc0923000 - 0xc09811c0   ( 377 kB)
    [    0.000000]       .data : 0xc0982000 - 0xc0a2e520   ( 690 kB)
    [    0.000000]        .bss : 0xc0a2e52c - 0xc0a7103c   ( 267 kB)
    [    0.000000] Preemptible hierarchical RCU implementation.
    [    0.000000] NR_IRQS:16 nr_irqs:16 16
    [    0.000000] OMAP clockevent source: timer1 at 31475 Hz
    [    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns
    [    0.000030] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000396] Architected cp15 timer(s) running at 5.90MHz (virt).
    [    0.000432] sched_clock: 56 bits at 5MHz, resolution 169ns, wraps every 2911033065472ns
    [    0.000440] Switching to timer-based delay loop
    [    0.001463] Console: colour dummy device 80x30
    [    0.001481] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
    [    0.001488] This ensures that you still see kernel messages. Please
    [    0.001494] update your kernel commandline.
    [    0.001506] Calibrating delay loop (skipped), value calculated using timer frequency.. 11.80 BogoMIPS (lpj=59016)
    [    0.001519] pid_max: default: 32768 minimum: 301
    [    0.001629] Security Framework initialized
    [    0.001683] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.001693] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.026089] CPU: Testing write buffer coherency: ok
    [    0.026347] /cpus/cpu@0 missing clock-frequency property
    [    0.026382] /cpus/cpu@1 missing clock-frequency property
    [    0.026394] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.026420] Setting up static identity map for 0x8068a628 - 0x8068a698
    [    0.080822] CPU1: Booted secondary processor
    [    0.080852] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.080977] Brought up 2 CPUs
    [    0.080993] SMP: Total of 2 processors activated (23.60 BogoMIPS).
    [    0.081000] CPU: All CPU(s) started in SVC mode.
    [    0.081423] devtmpfs: initialized
    [    0.082170] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.083890] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.097325] omap_hwmod: tptc0 using broken dt data from edma-controller
    [    0.097837] omap_hwmod: tptc1 using broken dt data from edma-controller
    [    0.269293] pinctrl core: initialized pinctrl subsystem
    [    0.270046] regulator-dummy: no parameters
    [    0.274429] NET: Registered protocol family 16
    [    0.276304] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.278393] cpuidle: using governor ladder
    [    0.278403] cpuidle: using governor menu
    [    0.325250] syscon 4a002000.tisysconcore: regmap [mem 0x4a002000-0x4a0026cf] registered
    [    0.325585] syscon 4a002e00.tisyscon: regmap [mem 0x4a002e00-0x4a002e7b] registered
    [    0.328430] OMAP GPIO hardware version 0.1
    [    0.334810] irq: no irq domain found for /ocp/pinmux@4a003400 !
    [    0.342286] platform 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000
    [    0.342592] platform 55020000.ipu: assigned reserved memory node ipu2_cma@95800000
    [    0.342893] platform 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
    [    0.358242] platform 41000000.dsp: assigned reserved memory node dsp2_cma@9f000000
    [    0.362730] No ATAGs?
    [    0.362758] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
    [    0.362767] hw-breakpoint: maximum watchpoint size is 8 bytes.
    [    0.365694] OMAP DMA hardware revision 0.0
    [    0.394029] bio: create slab <bio-0> at 0
    [    0.410226] edma-dma-engine edma-dma-engine.0: TI EDMA DMA engine driver
    [    0.416325] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver
    [    0.417115] evm_3v3_sd: 3300 mV
    [    0.417431] evm_3v3_sw: 3300 mV
    [    0.417496] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to find supply vin
    [    0.417682] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to register regulator: -517
    [    0.417701] platform fixedregulator-evm_3v3_sw: Driver reg-fixed-voltage requests probe deferral
    [    0.417952] aic_dvdd: 1800 mV
    [    0.418009] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to find supply vin
    [    0.418188] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to register regulator: -517
    [    0.418207] platform fixedregulator-aic_dvdd: Driver reg-fixed-voltage requests probe deferral
    [    0.418457] vmmcwl_fixed: 1800 mV
    [    0.418777] vtt_fixed: 1350 mV
    [    0.418825] reg-fixed-voltage fixedregulator-vtt: Failed to find supply vin
    [    0.419000] reg-fixed-voltage fixedregulator-vtt: Failed to register regulator: -517
    [    0.419018] platform fixedregulator-vtt: Driver reg-fixed-voltage requests probe deferral
    [    0.422547] vgaarb: loaded
    [    0.423004] i2c-core: driver [palmas] using legacy suspend method
    [    0.423014] i2c-core: driver [palmas] using legacy resume method
    [    0.423618] SCSI subsystem initialized
    [    0.424913] usbcore: registered new interface driver usbfs
    [    0.425086] usbcore: registered new interface driver hub
    [    0.425271] usbcore: registered new device driver usb
    [    0.427629] palmas 0-0058: IRQ missing: skipping irq request
    [    0.427983] palmas 0-0058: Muxing GPIO a, PWM 0, LED 0
    [    0.428133] prom_parse: Bad cell count for /ocp/i2c@48070000/tps659038@58
    [    0.430316] smps12: 850 <--> 1250 mV at 1030 mV
    [    0.433028] smps3: 850 <--> 1250 mV at 1350 mV
    [    0.434740] smps45: 850 <--> 1150 mV at 990 mV
    [    0.436422] smps6: 850 <--> 1250 mV at 1050 mV
    [    0.437968] smps7: 850 <--> 1060 mV at 970 mV
    [    0.439671] smps8: 850 <--> 1250 mV at 1000 mV
    [    0.441207] smps9: 1800 mV
    [    0.451647] ldo1: 1800 <--> 3300 mV at 3000 mV
    [    0.461102] ldo2: 3300 mV
    [    0.471128] ldo3: 1800 mV
    [    0.472036] LDO4: no parameters
    [    0.472630] LDO5: no parameters
    [    0.473250] LDO6: no parameters
    [    0.473858] LDO7: no parameters
    [    0.474457] LDO8: no parameters
    [    0.481190] ldo9: 1050 mV
    [    0.491144] ldoln: 1800 mV
    [    0.501219] ldousb: 3300 mV
    [    0.502151] regen1: no parameters
    [    0.502738] regen2: no parameters
    [    0.503460] sysen1: no parameters
    [    0.504052] sysen2: no parameters
    [    0.504308] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
    [    0.505193] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
    [    0.505261] omap_i2c 4807a000.i2c: could not find pctldev for node /ocp/padconf@4844a000/pinmux_i2c4_pins, deferring probe
    [    0.505277] platform 4807a000.i2c: Driver omap_i2c requests probe deferral
    [    0.505693] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
    [    0.505970] media: Linux media interface: v0.10
    [    0.506122] Linux video capture interface: v2.00
    [    0.506354] pps_core: LinuxPPS API ver. 1 registered
    [    0.506363] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [    0.506477] PTP clock support registered
    [    0.507950] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
    [    0.508399] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
    [    0.509433] omap-iommu 40d01000.mmu: 40d01000.mmu registered
    [    0.509548] omap-iommu 40d02000.mmu: 40d02000.mmu registered
    [    0.509650] omap-iommu 58882000.mmu: 58882000.mmu registered
    [    0.509757] omap-iommu 55082000.mmu: 55082000.mmu registered
    [    0.509923] omap-iommu 41501000.mmu: 41501000.mmu registered
    [    0.510031] omap-iommu 41502000.mmu: 41502000.mmu registered
    [    0.510825] Advanced Linux Sound Architecture Driver Initialized.
    [    0.512216] Switched to clocksource arch_sys_counter
    [    0.530778] NET: Registered protocol family 2
    [    0.531478] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
    [    0.531517] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
    [    0.531588] TCP: Hash tables configured (established 4096 bind 4096)
    [    0.531623] TCP: reno registered
    [    0.531636] UDP hash table entries: 256 (order: 1, 8192 bytes)
    [    0.531657] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
    [    0.531843] NET: Registered protocol family 1
    [    0.532111] RPC: Registered named UNIX socket transport module.
    [    0.532121] RPC: Registered udp transport module.
    [    0.532128] RPC: Registered tcp transport module.
    [    0.532135] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [    0.533286] hw perfevents: enabled with ARMv7 Cortex-A15 PMU driver, 7 counters available
    [    0.536218] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.646307] VFS: Disk quotas dquot_6.5.2
    [    0.646420] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
    [    0.647019] NFS: Registering the id_resolver key type
    [    0.647058] Key type id_resolver registered
    [    0.647067] Key type id_legacy registered
    [    0.647099] jffs2: version 2.2. (NAND) (SUMMARY)  c 2001-2006 Red Hat, Inc.
    [    0.647285] msgmni has been set to 982
    [    0.651193] alg: No test for stdrng (krng)
    [    0.651375] NET: Registered protocol family 38
    [    0.651404] io scheduler noop registered (default)
    [    0.651413] io scheduler deadline registered
    [    0.651451] io scheduler cfq registered
    [    0.657637] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
    [    0.696291] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
    [    0.696306] pci_bus 0000:00: root bus resource [io  0x1000-0x10000]
    [    0.696318] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
    [    0.696330] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
    [    0.696851] PCI: bus0: Fast back to back transfers disabled
    [    0.697093] PCI: bus1: Fast back to back transfers enabled
    [    0.697210] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
    [    0.697227] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
    [    0.697241] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.697263] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.701074] pbias_mmc_omap5: 1800 <--> 3000 mV at 3000 mV
    [    0.701862] abb_mpu: 1100 <--> 1210 mV
    [    0.702248] abb_ivahd: 1060 <--> 1250 mV
    [    0.702610] abb_dspeve: 1060 <--> 1250 mV
    [    0.702970] abb_gpu: 1060 <--> 1280 mV
    [    0.704071] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
    [    0.708536] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 299, base_baud = 3000000) is a 8250
    [    0.709316] 4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 300, base_baud = 3000000) is a 8250
    [    0.710093] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 301, base_baud = 3000000) is a 8250
    [    1.859703] console [ttyS2] enabled
    [    1.864034] 48066000.serial: ttyS4 at MMIO 0x48066000 (irq = 302, base_baud = 3000000) is a 8250
    [    1.873658] 48420000.serial: ttyS6 at MMIO 0x48420000 (irq = 303, base_baud = 3000000) is a 8250
    [    1.884235] omap_rng 48090000.rng: OMAP Random Number Generator ver. 20
    [    1.891382] [drm] Initialized drm 1.1.0 20060810
    [    1.906798] brd: module loaded
    [    1.915433] loop: module loaded
    [    1.918910] (hci_tty): inside hci_tty_init
    [    1.923403] (hci_tty): allocated 249, 0
    [    1.929669] ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
    [    1.936438] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
    [    1.945018] ahci 4a140000.sata: flags: 64bit ncq sntf stag pm led clo only pmp pio slum part ccc apst
    [    1.955488] scsi0 : ahci_platform
    [    1.959303] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 336
    [    1.968595] mtdoops: mtd device (mtddev=name/number) must be supplied
    [    1.980402] usbcore: registered new interface driver asix
    [    1.985991] usbcore: registered new interface driver ax88179_178a
    [    1.992558] usbcore: registered new interface driver cdc_ether
    [    1.998578] usbcore: registered new interface driver smsc95xx
    [    2.004506] usbcore: registered new interface driver net1080
    [    2.010328] usbcore: registered new interface driver cdc_subset
    [    2.016432] usbcore: registered new interface driver zaurus
    [    2.022226] usbcore: registered new interface driver cdc_ncm
    [    2.028337] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    [    2.034909] ehci-pci: EHCI PCI platform driver
    [    2.039515] ehci-omap: OMAP-EHCI Host Controller driver
    [    2.045314] usbcore: registered new interface driver cdc_wdm
    [    2.051159] usbcore: registered new interface driver usb-storage
    [    2.058299] mousedev: PS/2 mouse device common for all mice
    [    2.066014] i2c-core: driver [rtc-ds1307] using legacy suspend method
    [    2.072499] i2c-core: driver [rtc-ds1307] using legacy resume method
    [    2.079557] omap_rtc 48838000.rtcss: rtc core: registered 48838000.rtcss as rtc0
    [    2.087851] i2c /dev entries driver
    [    2.312248] ata1: SATA link down (SStatus 0 SControl 300)
    [    3.092270] omap_i2c 48072000.i2c: controller timed out
    [    3.112246] tvp5158 1-0058: i2c i/o error: rc == -110 (should be 1)
    [    4.112241] omap_i2c 48072000.i2c: controller timed out
    [    4.132243] tvp5158 1-0058: i2c i/o error: rc == -110 (should be 1)
    [    4.138538] tvp5158 1-0058: ERROR: Chip id is not TVP5158
    [    4.144912] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
    [    4.151040] vip 48970000.vip: No explicit pinctrl resources data.
    [    4.158157] vip 48970000.vip: loading firmware vpdma-1b8.bin
    [    4.164141] vpe 489d0000.vpe: Device registered as /dev/video0
    [    4.170162] Driver for 1-wire Dallas network protocol.
    [    4.176423] coproc iva_coproc: probe
    [    4.180134] Adding alias for supply vdd,iva_coproc -> vdd,4a0025cc.voltdm
    [    4.186980] vip 48970000.vip: VPDMA firmware loaded
    [    4.191974] vip1-s1: Port A enabled but no endpoints found
    [    4.197330] Adding alias for supply vbb,iva_coproc -> vbb,4a0025cc.voltdm
    [    4.204351] vip1-s0: Port B enabled but no endpoints found
    [    4.209686] vip1-s1: Port B enabled but no endpoints found[    4.216617] coproc iva_coproc: coproc_probe result=0
    [    4.221640] coproc dsp_coproc: probe
    [    4.225325] Adding alias for supply vdd,dsp_coproc -> vdd,4a0025e0.voltdm
    [    4.232143] Adding alias for supply vbb,dsp_coproc -> vbb,4a0025e0.voltdm
    [    4.240421] coproc dsp_coproc: coproc_probe result=0
    [    4.249668] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
    [    4.293347] ledtrig-cpu: registered to indicate activity on CPUs
    [    4.299679] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
    [    4.321897] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
    [    4.328215] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
    [    4.334636] alg: skcipher: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.342328] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.350472] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.363422] mmc0: host does not support reading read-only switch. assuming write-enable.
    [    4.363708] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
    [    4.379333] mmc0: new high speed SDHC card at address 1234
    [    4.386359] mmcblk0: mmc0:1234 SA04G 3.70 GiB
    [    4.392541]  mmcblk0: p1 p2
    [    4.409522] usbcore: registered new interface driver usbhid
    [    4.415171] usbhid: USB HID core driver
    [    4.420106]  remoteproc0: 58820000.ipu is available
    [    4.425080]  remoteproc0: Note: remoteproc is still under development and considered experimental.
    [    4.434093]  remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.444643]  remoteproc0: Direct firmware load failed with error -2
    [    4.450937]  remoteproc0: Falling back to user helper
    [    4.456133]  remoteproc1: 55020000.ipu is available
    [    4.461032]  remoteproc1: Note: remoteproc is still under development and considered experimental.
    [    4.470216]  remoteproc1: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.480770]  remoteproc1: Direct firmware load failed with error -2
    [    4.487188]  remoteproc2: 40800000.dsp is available
    [    4.492086]  remoteproc2: Note: remoteproc is still under development and considered experimental.
    [    4.501107]  remoteproc1: Falling back to user helper
    [    4.502252]  remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.502362]  remoteproc2: Direct firmware load failed with error -2
    [    4.502366]  remoteproc2: Falling back to user helper
    [    4.502732]  remoteproc3: 41000000.dsp is available
    [    4.502735]  remoteproc3: Note: remoteproc is still under development and considered experimental.
    [    4.502739]  remoteproc3: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.503036]  remoteproc3: Direct firmware load failed with error -2
    [    4.503038]  remoteproc3: Falling back to user helper
    [    4.567258] [sound/soc/soc-utils.c, snd_soc_dummy_probe, 137] Louis
    [    4.573576] [sound/soc/soc-core.c, snd_soc_register_platform, 4577] Louis, ASoC: platform register 'snd-soc-dummy'
    [    4.583985] [sound/soc/soc-core.c, snd_soc_add_platform, 4556] Louis, ASoC: Registered platform 'snd-soc-dummy'
    [    4.595721] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    4.603692] davinci-mcasp 48468000.mcasp: numevt will be ignored due to errata i868
    [    4.611390] [sound/soc/davinci/davinci-mcasp.c, davinci_mcasp_probe, 1930] Louis
    [    4.618900] [sound/soc/soc-generic-dmaengine-pcm.c, snd_dmaengine_pcm_register, 426] Louis
    [    4.627723] [sound/soc/soc-generic-dmaengine-pcm.c, snd_dmaengine_pcm_register, 438] Louis
    [    4.636041] [sound/soc/soc-core.c, snd_soc_add_platform, 4556] Louis, ASoC: Registered platform '48468000.mcasp'
    [    4.646272] [sound/soc/davinci/davinci-mcasp.c, davinci_mcasp_probe, 1938] Louis
    [    4.655330] oprofile: using timer interrupt.
    [    4.659681] nf_conntrack version 0.5.0 (7862 buckets, 31448 max)
    [    4.666168] ip_tables: (C) 2000-2006 Netfilter Core Team
    [    4.671575] TCP: cubic registered
    [    4.674920] Initializing XFRM netlink socket
    [    4.679218] NET: Registered protocol family 17
    [    4.683710] NET: Registered protocol family 15
    [    4.688240] Bridge firewalling registered
    [    4.692285] can: controller area network core (rev 20120528 abi 9)
    [    4.698554] NET: Registered protocol family 29
    [    4.703029] can: raw protocol (rev 20120528)
    [    4.707354] 8021q: 802.1Q VLAN Support v1.8
    [    4.711587] Key type dns_resolver registered
    [    4.715891] NET: Registered protocol family 41
    [    4.721039] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.voltdm
    [    4.727353] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.voltdm
    [    4.735400] Power Management for TI OMAP4+ devices.
    [    4.740450] ThumbEE CPU extension supported.
    [    4.744753] Registering SWP/SWPB emulation handler
    [    4.749562] SmartReflex Class3 initialized
    [    4.755192] vmmcwl_fixed: disabling
    [    4.758692] regulator-dummy: disabling
    [    4.762655] dmm 4e000000.dmm: workaround for errata i878 in use
    [    4.770344] dmm 4e000000.dmm: initialized all PAT entries
    [    4.777170] evm_3v3_sw: 3300 mV
    [    4.780442] evm_3v3_sw: supplied by sysen1
    [    4.784986] aic_dvdd: 1800 mV
    [    4.788082] aic_dvdd: supplied by evm_3v3_sw
    [    4.792622] vtt_fixed: 1350 mV
    [    4.795800] vtt_fixed: supplied by sysen2
    [    5.792245] omap_i2c 4807a000.i2c: controller timed out
    [    5.812311] pcf857x: probe of 3-0021 failed with error -110
    [    5.817968] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
    [    5.824122] [sound/soc/soc-core.c, soc_probe_link_components, 1466] Louis
    [    5.830941] [sound/soc/soc-core.c, soc_probe_link_components, 1466] Louis
    [    5.837776] [sound/soc/soc-core.c, soc_probe_link_components, 1466] Louis
    [    5.844703] [sound/soc/soc-core.c, soc_probe_link_components, 1466] Louis
    [    5.851520] [sound/soc/soc-core.c, soc_probe_link_components, 1489] Louis
    [    5.858352] [sound/soc/soc-core.c, soc_probe_platform, 1249] Louis
    [    5.864571] [sound/soc/soc-core.c, soc_probe_platform, 1256] Louis
    [    5.870777] [sound/soc/soc-core.c, soc_init_platform_debugfs, 317] Louis, before debugfs_create_dir(), platform->name: 48468000.mcasp
    [    5.882863] [sound/soc/soc-core.c, soc_probe_link_components, 1466] Louis
    [    5.890419] asoc-simple-card sound@0:  bt-sco-pcm <-> 48468000.mcasp mapping ok
    [    5.897786] asoc-simple-card sound@0: ASoC: no source widget found for HPLOUT
    [    5.904969] asoc-simple-card sound@0: ASoC: Failed to add route HPLOUT -> direct -> Headphone Jack
    [    5.913981] asoc-simple-card sound@0: ASoC: no source widget found for HPROUT
    [    5.921149] asoc-simple-card sound@0: ASoC: Failed to add route HPROUT -> direct -> Headphone Jack
    [    5.930162] asoc-simple-card sound@0: ASoC: no source widget found for LLOUT
    [    5.937255] asoc-simple-card sound@0: ASoC: Failed to add route LLOUT -> direct -> Line Out
    [    5.945656] asoc-simple-card sound@0: ASoC: no source widget found for RLOUT
    [    5.952749] asoc-simple-card sound@0: ASoC: Failed to add route RLOUT -> direct -> Line Out
    [    5.961137] asoc-simple-card sound@0: ASoC: no sink widget found for MIC3L
    [    5.968055] asoc-simple-card sound@0: ASoC: Failed to add route Mic Jack -> direct -> MIC3L
    [    5.976456] asoc-simple-card sound@0: ASoC: no sink widget found for MIC3R
    [    5.983374] asoc-simple-card sound@0: ASoC: Failed to add route Mic Jack -> direct -> MIC3R
    [    5.991762] asoc-simple-card sound@0: ASoC: no source widget found for Mic Bias
    [    5.999117] asoc-simple-card sound@0: ASoC: Failed to add route Mic Bias -> direct -> Mic Jack
    [    6.007784] asoc-simple-card sound@0: ASoC: no sink widget found for LINE1L
    [    6.014901] asoc-simple-card sound@0: ASoC: Failed to add route Line In -> direct -> LINE1L
    [    6.023307] asoc-simple-card sound@0: ASoC: no sink widget found for LINE1R
    [    6.030299] asoc-simple-card sound@0: ASoC: Failed to add route Line In -> direct -> LINE1R
    [    6.082241] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
    [    6.088366] davinci_mdio 48485000.mdio: detected phy mask e7c0fffe
    [    6.113069] libphy: 48485000.mdio: probed
    [    6.117101] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver unknown
    [    6.125156] davinci_mdio 48485000.mdio: phy[16]: device 48485000.mdio:10, driver unknown
    [    6.133296] davinci_mdio 48485000.mdio: phy[17]: device 48485000.mdio:11, driver unknown
    [    6.141422] davinci_mdio 48485000.mdio: phy[18]: device 48485000.mdio:12, driver unknown
    [    6.149597] davinci_mdio 48485000.mdio: phy[19]: device 48485000.mdio:13, driver unknown
    [    6.157889] davinci_mdio 48485000.mdio: phy[20]: device 48485000.mdio:14, driver unknown
    [    6.166049] davinci_mdio 48485000.mdio: phy[21]: device 48485000.mdio:15, driver unknown
    [    6.174209] davinci_mdio 48485000.mdio: phy[27]: device 48485000.mdio:1b, driver unknown
    [    6.183211] cpsw 48484000.ethernet: Detected MACID = 7c:ec:79:9c:14:5a
    [    6.190446] cpsw 48484000.ethernet: cpsw: Detected MACID = d0:b5:c2:30:b7:c1
    [    6.198366] omap_rtc 48838000.rtcss: setting system clock to 2000-01-01 00:00:04 UTC (946684804)
    [    6.207205] sr_init: No PMIC hook to init smartreflex
    [    6.212498] sr_init: platform driver register failed for SR
    [    6.227031] ALSA device list:
    [    6.230012]   #0: DRA7xx-EVM
    [    7.573514] EXT4-fs (mmcblk0p2): recovery complete
    [    7.584606] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    [    7.592780] VFS: Mounted root (ext4 filesystem) on device 179:2.
    [    7.599923] devtmpfs: mounted
    [    7.603161] Freeing unused kernel memory: 376K (c0923000 - c0981000)
    INIT: version 2.88 booting
    Starting udev
    [    8.142065] udevd[1166]: starting version 182
    [    8.856619]  remoteproc3: failed to load dra7-dsp2-fw.xe66
    [    8.911821]  remoteproc0: failed to load dra7-ipu1-fw.xem4
    [    8.975796]  remoteproc2: powering up 40800000.dsp
    [    8.984096]  remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 929770
    [    9.000497] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
    [    9.006383] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
    [    9.012297] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
    [    9.119753]  remoteproc2: remote processor 40800000.dsp is now up
    [    9.126429] virtio_rpmsg_bus virtio0: rpmsg host is online
    [    9.131957]  remoteproc2: registered virtio0 (type 7)
    [    9.137299] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x36
    [    9.145332] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x37
    [    9.153972] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x3b
    [    9.161002] rpmsg_rpc rpmsg2: probing service rpmsg-dce-dsp with src 1024 dst 59
    [    9.171051] rpmsg_rpc rpmsg2: published functions = 8
    [    9.470840]  remoteproc1: powering up 55020000.ipu
    [    9.482255]  remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 3484972
    [    9.489228] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
    [    9.581748]  remoteproc1: remote processor 55020000.ipu is now up
    [    9.588437] virtio_rpmsg_bus virtio1: rpmsg host is online
    [    9.594001]  remoteproc1: registered virtio1 (type 7)
    [    9.597174] virtio_rpmsg_bus virtio1: creating channel rpmsg-rpc addr 0x3b
    [    9.597370] rpmsg_rpc rpmsg3: probing service rpmsg-dce with src 1024 dst 59
    [    9.613661] rpmsg_rpc rpmsg3: published functions = 8
    udevd[1423]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory
    
    udevd[1424]: failed to execute '/etc/udev/scripts/mount.sh' '/etc/udev/scripts/mount.sh': No such file or directory
    
    [   10.222853] dwc3 48890000.usb: otg: primary host xhci-hcd.0.auto registered
    [   10.229850] dwc3 48890000.usb: otg: shared host xhci-hcd.0.auto registered
    [   10.236780] dwc3 48890000.usb: otg: can't start till gadget registers
    [   10.243749] dwc3 488d0000.usb: otg: primary host xhci-hcd.1.auto registered
    [   10.250741] dwc3 488d0000.usb: otg: shared host xhci-hcd.1.auto registered
    [   10.257655] dwc3 488d0000.usb: otg: can't start till gadget registers
    [   10.323963] Number of LUNs=8
    [   10.326862] Mass Storage Function, version: 2009/09/11
    [   10.332019] LUN: removable file: (no medium)
    [   10.336329] Number of LUNs=1
    [   10.339288] LUN: file: /dev/ram0
    [   10.342805] Number of LUNs=1
    [   10.345879] g_mass_storage gadget: Mass Storage Gadget, version: 2009/09/11
    [   10.352926] g_mass_storage gadget: userspace failed to provide iSerialNumber
    [   10.360013] g_mass_storage gadget: g_mass_storage ready
    [   10.365296] dwc3 48890000.usb: otg: gadget gadget registered
    [   10.371023] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
    [   10.377044] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
    [   10.385261] xhci-hcd xhci-hcd.0.auto: irq 425, io mem 0x48890000
    [   10.391543] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
    [   10.398447] random: nonblocking pool is initialized
    [   10.401577] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    [   10.401583] usb usb1: Product: xHCI Host Controller
    [   10.401588] usb usb1: Manufacturer: Linux 3.14.49 xhci-hcd
    [   10.401593] usb usb1: SerialNumber: xhci-hcd.0.auto
    [   10.430427] hub 1-0:1.0: USB hub found
    [   10.434284] hub 1-0:1.0: 1 port detected
    [   10.439122] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
    [   10.448573] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
    [   10.458099] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
    [   10.465022] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    [   10.472466] usb usb2: Product: xHCI Host Controller
    [   10.477367] usb usb2: Manufacturer: Linux 3.14.49 xhci-hcd
    [   10.482896] usb usb2: SerialNumber: xhci-hcd.0.auto
    [   10.488404] hub 2-0:1.0: USB hub found
    [   10.492204] hub 2-0:1.0: 1 port detected
    [   10.587622] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
    Starting Bootlog daemon: bootlogd: cannot allocate pseudo tty: No such file or directory
    bootlogd.
    ALSA: Restoring mixer settings...
    No state is present for card DRA7xxEVM
    Found hardware: "DRA7xx-EVM" "" "" "" ""
    Hardware is initialized using a generic method
    No state is present for card DRA7xxEVM
    Thu Sep  3 18:41:00 UTC 2015
    INIT: Entering runlevel: 5
    Configuring network interfaces... [   11.451355] net eth0: initializing cpsw version 1.15 (0)
    [   11.536151] net eth0: phy found : id is : 0x1410dd1
    [   11.548426] 8021q: adding VLAN 0 to HW filter on device eth0
    done.
    Starting system message bus: dbus.
    UIM SYSFS Node Not Found
    Starting telnet daemon.
    Starting tiipclad daemon
    GateMP support enabled on host
    
    Opened log file: lad.txt
    
    numProcessors = 5 id = 0 baseId = 0
    
    Spawned daemon: /usr/bin/lad_dra7xx
    
    .
    Starting rpcbind daemon...rpcbind: cannot create socket for udp6
    rpcbind: cannot create socket for tcp6
    done.
    creating NFS state directory: done
    starting statd: done
    NFS daemon support not enabled in kernel
    Starting syslogd/klogd: done
    Starting thttpd.
    [   12.402862] net eth1: initializing cpsw version 1.15 (0)
    [   12.485154] net eth1: phy found : id is : 0xff001653
    [   12.494330] 8021q: adding VLAN 0 to HW filter on device eth1
    [   12.510434] device eth0 entered promiscuous mode
    [   12.519099] device eth1 entered promiscuous mode
    [   12.526687] br0: port 2(eth1) entered forwarding state
    [   12.531860] br0: port 2(eth1) entered forwarding state
    [   12.552413] br0: port 2(eth1) entered disabled state
    Enabling thermal zones...
    *** Running User Application ***
    Stopping Bootlog daemon: bootlogd.
    
    root@wnc-cb:~# [   20.065894] omap_hwmod: mmu_ipu2: _wait_target_disable failed
    
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
     &ot@wnc-cb:~# aplay -r8000 -D plughw:0,0 i2s_1k_tone_16_bits_8k_sample_rate.wav
    [1] 1689
    root@wnc-cb:~# Playing WAVE 'i2s_1k_tone_16_bits_8k_sample_rate.wav' : Signed 16 bit Little Endian, Rate 8000 Hz, Mono
    
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~# omapconf show mcasp3
    OMAPCONF (rev v1.72 built Thu Sep 3 23:45:43 IST 2015)
    
    HW Platform:
      Generic DRA74X (Flattened Device Tree)
      DRA75X ES1.1 GP Device (STANDARD performance (1.0GHz))
      TPS659038  ES2.2
    
    SW Build Details:
      Build:
        Version:  _____                    _____           _         _
      Kernel:
        Version: 3.14.49
        Author: root@louis-VirtualBox
        Toolchain: gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03)
        Type: #74 SMP PREEMPT
        Date: Tue Jul 25 17:11:36 CST 2017
    
    |---------------------------------------------|
    | Data Ports and Buffers                      |
    |---------------------------------------------|
    | Port                   | DATA bus           |
    | Transmit DMA           |                    |
    |   DMA request          | Enabled            |
    |   Status               | No error           |
    | Receive DMA            |                    |
    |   DMA request          | Enabled            |
    |   Status               | No error           |
    | Transmit Buffer (XBUF) |                    |
    |   Status               | No error           |
    | Receive Buffer (RBUF)  |                    |
    |   Status               | No error           |
    | Write FIFO (WFIFO)     |                    |
    |   State                | Enabled            |
    |   Threshold            | 25 samples         |
    |   Level                | 59 samples in FIFO |
    | Read FIFO (RFIFO)      |                    |
    |   State                | Disabled           |
    |   Threshold            | 16 samples         |
    |   Level                | 0 samples in FIFO  |
    |---------------------------------------------|
    
    |----------------------------------------|
    | Control                                |
    |----------------------------------------|
    | Transmit State-Machine |               |
    |   State                | Active        |
    | Transmit Sequencer     |               |
    |   Enabled Slots        | 2             |
    |   Active Slots         | 1             |
    |   Active Slots Mask    | 0x00000001    |
    |   Current Slot         | 0             |
    | Receive State-Machine  |               |
    |   State                | Held in reset |
    | Receive Sequencer      |               |
    |   Enabled Slots        | 2             |
    |   Active Slots         | 1             |
    |   Active Slots Mask    | 0x00000001    |
    |   Current Slot         | Inactive      |
    |----------------------------------------|
    
    |-----------------------------------------------------|
    | Clocks                                              |
    |-----------------------------------------------------|
    | Transmit Bit Clock        |                         |
    |   State                   | Running                 |
    |   Divider                 | Divide-by 32            |
    |   Source                  | Internal                |
    |   Polarity                | Driven on rising edge   |
    | Transmit High-Speed Clock |                         |
    |   State                   | Running                 |
    |   Divider                 | Divide-by 1             |
    |   Source                  | External (AHCLKX pin)   |
    |   Polarity                | Non-inverted            |
    | Receive Bit Clock         |                         |
    |   State                   | Held in reset           |
    |   Divider                 | Divide-by 32            |
    |   Source                  | Internal                |
    |   Polarity                | Samples on falling edge |
    | Sync Mode                 | Synchronous to TX       |
    | Idle Mode                 | No-idle                 |
    |-----------------------------------------------------|
    
    |----------------------------------------------------|
    | Frame Sync Generator                               |
    |----------------------------------------------------|
    | Transmit Frame Sync |                              |
    |   Generator State   | Active                       |
    |   Source            | Internal                     |
    |   Polarity          | Frame starts on falling edge |
    |   Pulse Width       | Single word                  |
    |   Slot Count        | 2 (TDM)                      |
    |   Data Delay        | 1-bit                        |
    |   Status            | No error                     |
    | Receive Frame Sync  |                              |
    |   Generator State   | Held in reset                |
    |   Source            | Internal                     |
    |   Polarity          | Frame starts on falling edge |
    |   Pulse Width       | Single word                  |
    |   Slot Count        | 2 (TDM)                      |
    |   Data Delay        | 1-bit                        |
    |   Status            | No error                     |
    | Sync Mode           | Synchronous to TX            |
    |----------------------------------------------------|
    
    |-----------------------------------------|
    | Format Units                            |
    |-----------------------------------------|
    | Transmit Format Unit |                  |
    |   Slot Size          | 16 bits          |
    |   Bit Mask           | 0x0000FFFF       |
    |   Padding            | Pad with 0       |
    |   Right-Rotation     | 16 bit positions |
    |   Bitstream Order    | MSB first        |
    | Receive Format Unit  |                  |
    |   Slot Size          | 16 bits          |
    |   Bit Mask           | 0x0000FFFF       |
    |   Padding            | Pad with 0       |
    |   Right-Rotation     | 0 bit positions  |
    |   Bitstream Order    | MSB first        |
    |-----------------------------------------|
    
    |----------------------------------|
    | Serializers                      |
    |----------------------------------|
    | Transmit Serializers | Active    |
    | Receive Serializers  | Cleared   |
    | Serializer 0         |           |
    |   Mode               | Receive   |
    |   Inactive State     | Hi-Z      |
    | Serializer 1         |           |
    |   Mode               | Transmit  |
    |   Inactive State     | Logic Low |
    | Serializer 2         |           |
    |   Mode               | Inactive  |
    |   Inactive State     | Hi-Z      |
    | Serializer 3         |           |
    |   Mode               | Inactive  |
    |   Inactive State     | Hi-Z      |
    |----------------------------------|
    
    |--------------------------------------------|
    | Pin Control                                |
    |--------------------------------------------|
    | AFSR            |                          |
    |   Functionality | Receive Frame Sync       |
    |   Direction     | Output                   |
    | ACLKR           |                          |
    |   Functionality | Receive Bit Clock        |
    |   Direction     | Output                   |
    | AFSX            |                          |
    |   Functionality | Transmit Frame Sync      |
    |   Direction     | Output                   |
    | ACLKX           |                          |
    |   Functionality | Transmit Bit Clock       |
    |   Direction     | Output                   |
    | AHCLKX          |                          |
    |   Functionality | Transmit High-Freq Clock |
    |   Direction     | Input                    |
    | AXR0            |                          |
    |   Functionality | TX/RX Data Channel 0     |
    |   Direction     | Input                    |
    | AXR1            |                          |
    |   Functionality | TX/RX Data Channel 1     |
    |   Direction     | Output                   |
    | AXR2            |                          |
    |   Functionality | TX/RX Data Channel 2     |
    |   Direction     | Input                    |
    | AXR3            |                          |
    |   Functionality | TX/RX Data Channel 3     |
    |   Direction     | Input                    |
    |--------------------------------------------|
    
    omapconf: powerdm_deinit(): cpu not supported!!!
    omapconf: clockdm_deinit(): cpu not supported!!!
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~# omapconf show mcasp3
    OMAPCONF (rev v1.72 built Thu Sep 3 23:45:43 IST 2015)
    
    HW Platform:
      Generic DRA74X (Flattened Device Tree)
      DRA75X ES1.1 GP Device (STANDARD performance (1.0GHz))
      TPS659038  ES2.2
    
    SW Build Details:
      Build:
        Version:  _____                    _____           _         _
      Kernel:
        Version: 3.14.49
        Author: root@louis-VirtualBox
        Toolchain: gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03)
        Type: #74 SMP PREEMPT
        Date: Tue Jul 25 17:11:36 CST 2017
    
    |---------------------------------------------|
    | Data Ports and Buffers                      |
    |---------------------------------------------|
    | Port                   | DATA bus           |
    | Transmit DMA           |                    |
    |   DMA request          | Enabled            |
    |   Status               | No error           |
    | Receive DMA            |                    |
    |   DMA request          | Enabled            |
    |   Status               | No error           |
    | Transmit Buffer (XBUF) |                    |
    |   Status               | No error           |
    | Receive Buffer (RBUF)  |                    |
    |   Status               | No error           |
    | Write FIFO (WFIFO)     |                    |
    |   State                | Enabled            |
    |   Threshold            | 25 samples         |
    |   Level                | 54 samples in FIFO |
    | Read FIFO (RFIFO)      |                    |
    |   State                | Disabled           |
    |   Threshold            | 16 samples         |
    |   Level                | 0 samples in FIFO  |
    |---------------------------------------------|
    
    |----------------------------------------|
    | Control                                |
    |----------------------------------------|
    | Transmit State-Machine |               |
    |   State                | Active        |
    | Transmit Sequencer     |               |
    |   Enabled Slots        | 2             |
    |   Active Slots         | 1             |
    |   Active Slots Mask    | 0x00000001    |
    |   Current Slot         | 1             |
    | Receive State-Machine  |               |
    |   State                | Held in reset |
    | Receive Sequencer      |               |
    |   Enabled Slots        | 2             |
    |   Active Slots         | 1             |
    |   Active Slots Mask    | 0x00000001    |
    |   Current Slot         | Inactive      |
    |----------------------------------------|
    
    |-----------------------------------------------------|
    | Clocks                                              |
    |-----------------------------------------------------|
    | Transmit Bit Clock        |                         |
    |   State                   | Running                 |
    |   Divider                 | Divide-by 32            |
    |   Source                  | Internal                |
    |   Polarity                | Driven on rising edge   |
    | Transmit High-Speed Clock |                         |
    |   State                   | Running                 |
    |   Divider                 | Divide-by 1             |
    |   Source                  | External (AHCLKX pin)   |
    |   Polarity                | Non-inverted            |
    | Receive Bit Clock         |                         |
    |   State                   | Held in reset           |
    |   Divider                 | Divide-by 32            |
    |   Source                  | Internal                |
    |   Polarity                | Samples on falling edge |
    | Sync Mode                 | Synchronous to TX       |
    | Idle Mode                 | No-idle                 |
    |-----------------------------------------------------|
    
    |----------------------------------------------------|
    | Frame Sync Generator                               |
    |----------------------------------------------------|
    | Transmit Frame Sync |                              |
    |   Generator State   | Active                       |
    |   Source            | Internal                     |
    |   Polarity          | Frame starts on falling edge |
    |   Pulse Width       | Single word                  |
    |   Slot Count        | 2 (TDM)                      |
    |   Data Delay        | 1-bit                        |
    |   Status            | No error                     |
    | Receive Frame Sync  |                              |
    |   Generator State   | Held in reset                |
    |   Source            | Internal                     |
    |   Polarity          | Frame starts on falling edge |
    |   Pulse Width       | Single word                  |
    |   Slot Count        | 2 (TDM)                      |
    |   Data Delay        | 1-bit                        |
    |   Status            | No error                     |
    | Sync Mode           | Synchronous to TX            |
    |----------------------------------------------------|
    
    |-----------------------------------------|
    | Format Units                            |
    |-----------------------------------------|
    | Transmit Format Unit |                  |
    |   Slot Size          | 16 bits          |
    |   Bit Mask           | 0x0000FFFF       |
    |   Padding            | Pad with 0       |
    |   Right-Rotation     | 16 bit positions |
    |   Bitstream Order    | MSB first        |
    | Receive Format Unit  |                  |
    |   Slot Size          | 16 bits          |
    |   Bit Mask           | 0x0000FFFF       |
    |   Padding            | Pad with 0       |
    |   Right-Rotation     | 0 bit positions  |
    |   Bitstream Order    | MSB first        |
    |-----------------------------------------|
    
    |----------------------------------|
    | Serializers                      |
    |----------------------------------|
    | Transmit Serializers | Active    |
    | Receive Serializers  | Cleared   |
    | Serializer 0         |           |
    |   Mode               | Receive   |
    |   Inactive State     | Hi-Z      |
    | Serializer 1         |           |
    |   Mode               | Transmit  |
    |   Inactive State     | Logic Low |
    | Serializer 2         |           |
    |   Mode               | Inactive  |
    |   Inactive State     | Hi-Z      |
    | Serializer 3         |           |
    |   Mode               | Inactive  |
    |   Inactive State     | Hi-Z      |
    |----------------------------------|
    
    |--------------------------------------------|
    | Pin Control                                |
    |--------------------------------------------|
    | AFSR            |                          |
    |   Functionality | Receive Frame Sync       |
    |   Direction     | Output                   |
    | ACLKR           |                          |
    |   Functionality | Receive Bit Clock        |
    |   Direction     | Output                   |
    | AFSX            |                          |
    |   Functionality | Transmit Frame Sync      |
    |   Direction     | Output                   |
    | ACLKX           |                          |
    |   Functionality | Transmit Bit Clock       |
    |   Direction     | Output                   |
    | AHCLKX          |                          |
    |   Functionality | Transmit High-Freq Clock |
    |   Direction     | Input                    |
    | AXR0            |                          |
    |   Functionality | TX/RX Data Channel 0     |
    |   Direction     | Input                    |
    | AXR1            |                          |
    |   Functionality | TX/RX Data Channel 1     |
    |   Direction     | Output                   |
    | AXR2            |                          |
    |   Functionality | TX/RX Data Channel 2     |
    |   Direction     | Input                    |
    | AXR3            |                          |
    |   Functionality | TX/RX Data Channel 3     |
    |   Direction     | Input                    |
    |--------------------------------------------|
    
    omapconf: powerdm_deinit(): cpu not supported!!!
    omapconf: clockdm_deinit(): cpu not supported!!!
    root@wnc-cb:~# cat /proc/asound/card0/pcm0p/sub0/status
    state: RUNNING
    owner_pid   : 1689
    trigger_time: 1441305740.293928140
    tstamp      : 1441305746.714149808
    delay       : 3250
    avail       : 750
    avail_max   : 3000
    -----
    hw_ptr      : 62750
    appl_ptr    : 66000
    root@wnc-cb:~#
    root@wnc-cb:~# cat /proc/asound/card0/pcm0p/sub0/status
    state: RUNNING
    owner_pid   : 1689
    trigger_time: 1441305740.293928140
    tstamp      : 1441305747.892990096
    delay       : 3750
    avail       : 250
    avail_max   : 1000
    -----
    hw_ptr      : 74250
    appl_ptr    : 78000
    root@wnc-cb:~# cat /proc/asound/card0/pcm0p/sub0/status
    state: DRAINING
    owner_pid   : 1689
    trigger_time: 1441305740.293928140
    tstamp      : 1441305748.372915338
    delay       : 1050
    avail       : 2950
    avail_max   : 2950
    -----
    hw_ptr      : 78950
    appl_ptr    : 80000
    root@wnc-cb:~# cat /proc/asound/card0/pcm0p/sub0/status
    closed
    [1]+  Done                    aplay -r8000 -D plughw:0,0 i2s_1k_tone_16_bits_8k_sample_rate.wav
    root@wnc-cb:~# cat /proc/asound/card0/pcm0p/sub0/status
    closed
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~# cat /proc/asound/card0/pcm0p/sub0/status
    closed
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    root@wnc-cb:~#
    

    2. What is "sleep pin control status"? How do I cancel "sleep pin control status" in DTS?

    Thank you.

    BRs

    Louis

  • Louis,

    The output of the "omapconf show mcasp3" command seems to indicate that McASP3 is configured as master. Since this is the kernel 3.14, I assume you are running the aplay command on the carrier board where McASP3 is supposed to be slave.

    Could you share the relevant dts/dtsi files for the carrier board? I suspect mcasp3 is marked as the master in the simple card.

    The pinmux settings of the FSX and ACLKX pins might also be wrong, make sure they are marked as inputs in the carrier board, and as outputs in the adapt board.

    Also, make sure that you run arecord on the adapt board before running aplay on the carrier board, because the slave McASP needs the external clocks to run.

    Regarding #2 - it's applicable only if the mcasp3 node has a pnctrl-names property called "sleep".

  • Hi Misael,

    I'm in debug process, so current status Carrier Board works independent, that is, Carrier Board will be Master. Adapt Board does not connect with Carrier Board.

    And AXR1 will be Tx, AXR0 will be Rx.

    The attached file is my DTS

    6888.dra7-evm.dts.txt
    /*
     * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    /dts-v1/;
    
    #include "dra74x.dtsi"
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clk/ti-dra7-atl.h>
    #include <dt-bindings/pinmux/mux_dra7xx.h>
    
    / {
    	model = "TI DRA742 Louis 20170725 10:00";
    	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
    	
    	version = "20161109" ;
    	
    	memory {
    		device_type = "memory";
    		//reg = <0x80000000 0x60000000>; /* 1536 MB */							
    		//reg = <0x80000000 0x80000000>; /* 2048 MB */
    		reg = <0x80000000 0x20000000>; /* 512 MB */
    	};
    
    
    	leds {
    		pinctrl-names = "default";
    		pinctrl-0 = <&user_leds_default>;
    
    		compatible = "gpio-leds";
    
    		led@1 {
    			label = "FPGA_EN";
    			gpios = <&gpio8 23 GPIO_ACTIVE_HIGH>;
    			linux,default-trigger = "none";
    			default-state = "on";
    		};
    	};
    
    	reserved_mem: reserved-memory {
    		#address-cells = <1>;
    		#size-cells = <1>;
    		ranges;
    
    		ipu2_cma_pool: ipu2_cma@95800000 {
    			compatible = "shared-dma-pool";
    			reg = <0x95800000 0x3800000>;
    			reusable;
    			status = "okay";
    		};
    
    		dsp1_cma_pool: dsp1_cma@99000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x99000000 0x4000000>;
    			reusable;
    			status = "okay";
    		};
    
    		ipu1_cma_pool: ipu1_cma@9d000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x9d000000 0x2000000>;
    			reusable;
    			status = "okay";
    		};
    
    		dsp2_cma_pool: dsp2_cma@9f000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x9f000000 0x800000>;
    			reusable;
    			status = "okay";
    		};
    	};
    
    	extcon_usb1: extcon_usb1 {
    		status = "ok";
    		compatible = "linux,extcon-usb-gpio";
    		//id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
    		id-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
    	};
    
    	extcon_usb2: extcon_usb2 {
    		status = "ok";
    		compatible = "linux,extcon-usb-gpio";
    		//id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
    		id-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
    	};
    
    	evm_3v3_sd: fixedregulator-sd {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sd";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	evm_3v3_sw: fixedregulator-evm_3v3_sw {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sw";
    		vin-supply = <&sysen1>;
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	aic_dvdd: fixedregulator-aic_dvdd {
    		/* TPS77018DBVT */
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd";
    		vin-supply = <&evm_3v3_sw>;
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    	};
    
    	vmmcwl_fixed: fixedregulator-mmcwl {
    		compatible = "regulator-fixed";
    		regulator-name = "vmmcwl_fixed";
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    		//gpio = <&gpio5 8 0>;	/* gpio5_8 */
    		startup-delay-us = <70000>;
    		enable-active-high;
    	};
    
    /*
    	kim {
    		compatible = "kim";
    		nshutdown_gpio = <132>;
    		dev_name = "/dev/ttyS2";
    		flow_cntrl = <1>;
    		baud_rate = <3686400>;
    	};
    
    	btwilink {
    		compatible = "btwilink";
    	};
    */
    	vtt_fixed: fixedregulator-vtt {
    		compatible = "regulator-fixed";
    		regulator-name = "vtt_fixed";
    		regulator-min-microvolt = <1350000>;
    		regulator-max-microvolt = <1350000>;
    		regulator-always-on;
    		regulator-boot-on;
    		enable-active-high;
    		vin-supply = <&sysen2>;
    		//gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
    	};
    
    	aliases {
    		display0 = &hdmi0;
    		sound0 = &snd0;
    		sound1 = &hdmi;
    	};
    
    	hdmi0: connector@1 {
    		compatible = "hdmi-connector";
    		label = "hdmi";
    
    		type = "a";
    
    		port {
    			hdmi_connector_in: endpoint {
    				remote-endpoint = <&tpd12s015_out>;
    			};
    		};
    	};
    
    	tpd12s015: encoder@1 {
    		compatible = "ti,dra7evm-tpd12s015";
    		status = "disabled";
    
    		pinctrl-names = "i2c", "ddc";
    		pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
    		pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
    
    		ddc-i2c-bus = <&i2c2>;
    		mcasp-gpio = <&mcasp8>;
    
    		gpios = <&pcf_hdmi 4 0>,	/* P4, CT CP HPD */
    			<&pcf_hdmi 5 0>,	/* P5, LS OE */
    			<&gpio7 12 0>;	/* gpio7_12/sp1_cs2, HPD */
    
    		ports {
    			#address-cells = <1>;
    			#size-cells = <0>;
    
    			port@0 {
    				reg = <0>;
    
    				tpd12s015_in: endpoint@0 {
    					remote-endpoint = <&hdmi_out>;
    				};
    			};
    
    			port@1 {
    				reg = <1>;
    
    				tpd12s015_out: endpoint@0 {
    					remote-endpoint = <&hdmi_connector_in>;
    				};
    			};
    		};
    	};
    
        ocp {
            gpu: gpu@0x56000000 {
                gpu0-voltdm = <&voltdm_gpu>;
            };
        };
    
    	btsco: btsco@0 {
    		#sound-dai-cells = <0>;
    		status = "okay";
    		compatible = "linux,bt-sco-audio";
    	};
    
    
            snd0: sound@0 {
                    compatible = "simple-audio-card";
                    simple-audio-card,name = "DRA7xx-EVM";
    #if 0
    		/* we do not have codec */
    		simple-audio-card,mclk-fs = <256>;
    #endif
                    simple-audio-card,widgets =
                            "Headphone", "Headphone Jack",
                            "Line", "Line Out",
                            "Microphone", "Mic Jack",
                            "Line", "Line In";
                    simple-audio-card,routing =
                            "Headphone Jack",       "HPLOUT",
                            "Headphone Jack",       "HPROUT",
                            "Line Out",             "LLOUT",
                            "Line Out",             "RLOUT",
                            "MIC3L",                "Mic Jack",
                            "MIC3R",                "Mic Jack",
                            "Mic Jack",             "Mic Bias",
                            "LINE1L",               "Line In",
                            "LINE1R",               "Line In";
    		status = "okay";
    
    #if 1
    		simple-audio-card,dai-link@0 {
    			format = "i2s";
    			bitclock-master = <&sound0_master>;
    			frame-master = <&sound0_master>;
    			bitclock-inversion;
    
    			sound0_master: cpu {
    				sound-dai = <&mcasp3>;
    				system-clock-frequency = <8192000>;
    			};
    
    			codec {
    				sound-dai = <&btsco>;
    			};
    		};
    #else
                    simple-audio-card,format = "i2s";
                    simple-audio-card,bitclock-master = <&sound0_master>;
                    simple-audio-card,frame-master = <&sound0_master>;
                    simple-audio-card,bitclock-inversion;
    
                    sound0_master: simple-audio-card,cpu {
                            sound-dai = <&mcasp3>;
                            system-clock-frequency = <11289600>;
                    };  
    
                    simple-audio-card,codec {
                            sound-dai = <&btsco>;
                            clocks = <&atl_clkin2_ck>;
                    };
    #endif
            };
    };
    
    &dra7_pmx_core {
    
        // 20161109 For CB ver.F
    	cpsw_default: cpsw_default {
    		pinctrl-single,pins = <
    			// Slave 1 
    			
    			0x250 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_tclk.rgmii0_tclk W9 
    			0x254 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_tctl.rgmii0_tctl V9 
    			0x258 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td3.rgmii0_td3  V7 
    			0x25c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td2.rgmii0_td2  U7
    			0x260 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td1.rgmii0_td1 V6 
    			0x264 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td0.rgmii0_td0 U6 
    			0x268 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rmii0_rclk.rmii0_rclk U5 
    			0x26c (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rctl.rgmii0_rctl V5 
    			0x270 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd3.rgmii0_rd3 V4 
    			0x274 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd2.rgmii0_rd2 V3 
    			0x278 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd1.rgmii0_rd1 Y2 
    			0x27c (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd0.rgmii0_rd0 W2 
    			
    			
    			// Slave 2 
    			0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d12.rgmii1_tclk D5 
    			0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d13.rgmii1_tctl C2 
    			0x1a0 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d14.rgmii1_td3 C3 
    			0x1a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d15.rgmii1_td2 C4 
    			0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d16.rgmii1_td1 B2 
    			0x1ac (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d17.rgmii1_td0 D6 
    			0x1b0 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d18.rgmii1_rclk C5 
    			0x1b4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d19.rgmii1_rctl A3 
    			0x1b8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d20.rgmii1_rd3 B3 
    			0x1bc (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d21.rgmii1_rd2 B4 
    			0x1c0 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d22.rgmii1_rd1 B5 
    			0x1c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d23.rgmii1_rd0 A4
    		>;
    	};
    
    	
    	uart1_pins: pinmux_uart1_pins {
    		pinctrl-single,pins = <		
    
    #if 1
    			MCASP3_AXR0	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mcasp3_axr0, mode 0 */	// decidated			B19, 0x32C
    			MCASP3_AXR1	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mcasp3_axr1, mode 0 */	// decidated			C17, 0x330
    			MCASP3_ACLKX	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mcasp3_aclkr, */	//			B18, 0x324
    			MCASP3_FSX	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mcasp3_fsr, */	//			F15, 0x328
    #endif
    
    			UART1_RXD		(WAKEUP_EN | PIN_INPUT | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
    			UART1_TXD		(PIN_OUTPUT | MUX_MODE0)		/* uart1_txd.uart1_txd */		
    			UART1_CTSN	(PIN_OUTPUT | MUX_MODE0)			/* uart1_ctsn.uart1_ctsn */
    			UART1_RTSN	(PIN_INPUT | MUX_MODE0) 			/* uart1_rtsn.uart1_rtsn */
    
    			/* Can not do pin defines in I2C section */
    			/* Move all the I2C pin defines here */
    			// I2C1 controls
    			VIN2A_D0	(PIN_INPUT | MUX_MODE14)				 /* vin2a_d0.gpio4_1 */
    			VIN2A_D1	(PIN_INPUT | MUX_MODE14)				 /* vin2a_d1.gpio4_2 */	
    			// I2C4 controls
    			VIN1A_D7	(PIN_INPUT | MUX_MODE14)				 /* vin1a_d7.gpio3_11 */
    			VIN1A_D8	(PIN_INPUT | MUX_MODE14)				 /* vin1a_d8.gpio3_12 */
    			
    			//I2C4 PIN defines		
    			//MMC1_SDCD (PIN_INPUT | MUX_MODE4)  /* mmc1_sdcd.i2c4_sda -> 4 */
    			//MMC1_SDWP (PIN_INPUT | MUX_MODE4)  /* mmc1_sdwp.i2c4_scl -> 4 */
    			//I2C4 as GPIO		
    			MMC1_SDCD (PIN_INPUT | MUX_MODE14)  /* mmc1_sdcd.gpio?_?? */
    			MMC1_SDWP (PIN_INPUT | MUX_MODE14)  /* mmc1_sdwp.gpio?_?? */	
    
    			//I2C5 as GPIO for 7-segment display, Carrier Board hardware ver #F use i2c5
    			GPMC_A4 (PIN_INPUT | MUX_MODE7) /* gpmc_a4.i2c5_scl -> 7 */
    			GPMC_A5 (PIN_INPUT | MUX_MODE7) /* gpmc_a5.i2c5_sda -> 7 */
    
    			// POWINGING_SEQUENCE
    			// MD_12VPA_EN
    			GPMC_A10		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a10.gpio2_0 */
    			// MD_12VPB_EN
    			GPMC_A11		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a11.gpio2_1 */
    			// SOC_POWER_ON
    			GPMC_A12		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a12.gpio2_2 */
    #if 1       // 20161109 For CB ver.F			
    			// AB_VERSION
    			GPMC_A13		(PIN_INPUT | MUX_MODE14)		/* gpmc_a13.gpio2_3 */
    			GPMC_A14		(PIN_INPUT | MUX_MODE14)		/* gpmc_a14.gpio2_4 */
    			GPMC_A15		(PIN_INPUT | MUX_MODE14)		/* gpmc_a15.gpio2_5 */
    			GPMC_A16		(PIN_INPUT | MUX_MODE14)		/* gpmc_a16.gpio2_6 */
    
    			// CB_VERSION
    			GPMC_A13		(PIN_INPUT | MUX_MODE14)		/* gpmc_a13.gpio2_7 */
    			GPMC_A14		(PIN_INPUT | MUX_MODE14)		/* gpmc_a14.gpio2_8 */
    			GPMC_A15		(PIN_INPUT | MUX_MODE14)		/* gpmc_a15.gpio2_9 */
    			GPMC_A16		(PIN_INPUT | MUX_MODE14)		/* gpmc_a16.gpio2_10 */
    #endif
    							
    			// SOC_REST_EN
    			VIN1A_D2		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d2.gpio3_6 */
    
    			// BOOT MODE				
    			MMC3_DAT1		(PIN_INPUT | MUX_MODE14)		/* mmc3_dat1.gpio7_0 */
    			MMC3_DAT2		(PIN_INPUT | MUX_MODE14)		/* mmc3_dat2.gpio7_1 */	
    	
    			// DEBUG MESSAGE MUX CONTROL
    		  	VIN2A_DE0		(PIN_OUTPUT | MUX_MODE14)		/* vin2a_de0.gpio3_29  ==> 0x4A00_3558  ==> 0x1558 ==> 0x158 */	 
    
    		 	// LGA_SYSBOOT_1, _2, _3, _5
    		 	VIN1A_D21		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d21.gpio3_25	*/
    		 	VIN1A_D22		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d22.gpio3_26 */
    		 	USB2_DRVVBUS		(PIN_OUTPUT | MUX_MODE14)		/* usb2_drvvbus.gpio6_13 */
    		 	//GPMC_A25		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a25.gpio2_15 */
    		 	
    		 	// SATA_PATH_SELECT
    		 	GPMC_A6			(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a6.gpio1_28 */
                            // SATA_RST_N
                            GPIO6_14		(PIN_OUTPUT | MUX_MODE14)
    
    
    			// Carrier Board control Adapt Board INA226 chip x 5, only for iMX6, use i2c2, gpio5_2 & gpio5_3 both need in gpio input
    			MCASP1_AXR0 (PIN_INPUT | MUX_MODE14)	/* mcasp1_axr0.gpio5_2 -> 10 */
    			MCASP1_AXR1 (PIN_INPUT | MUX_MODE14)	/* mcasp1_axr1.gpio5_3 -> 10 */
    			
    			0x408	(PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
    			0x40c	(PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
    
    //=================================================================================							
    		>;
    	};
    	
    	user_leds_default: user_leds_default {
    		pinctrl-single,pins = <
    			0x238 (PIN_OUTPUT | MUX_MODE14)	/* vout1_d23.gpio8_23 A10 FPGA_EN */	
    		>;
    	};
    	
    	uart2_pins: pinmux_uart2_pins {
    		pinctrl-single,pins = <
    			UART2_RXD		(WAKEUP_EN | PIN_INPUT | MUX_MODE4)	/* uart2_rxd.uart2_rxd */
    			UART2_TXD		(PIN_OUTPUT | MUX_MODE4)		/* uart2_txd.uart2_txd */		
    		>;
    	};	
    	
    	uart3_pins: pinmux_uart3_pins {
    		pinctrl-single,pins = <
    			0x3f8 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* uart2_ctsn.uart3_rxd */
    			0x3fc (PIN_OUTPUT | MUX_MODE1)			/* uart2_rtsn.uart3_txd */			
    		>;
    	};
    
    //   Socket board
    
    //	uart3_pins: pinmux_uart3_pins {
    //		pinctrl-single,pins = <
    //			0x34c (PIN_INPUT_PULLUP | PIN_INPUT | MUX_MODE4)	/* mcasp5_axr0.uart3_rxd */
    //			0x350 (PIN_OUTPUT | MUX_MODE4)	/* mcasp5_axr1.uart3_txd */			
    //		>;
    //	};
    
    	uart5_pins: pinmux_uart5_pins {
    		pinctrl-single,pins = <
    			VOUT1_D0 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* vout1_d0.uart5_rxd */
    			VOUT1_D1 (PIN_OUTPUT | MUX_MODE2)						/* vout1_d1.uart5_txd */
    			VOUT1_D3 (PIN_OUTPUT | MUX_MODE14)					/* vout1_d3.gpio8_3 */
    			VOUT1_D4 (PIN_OUTPUT | MUX_MODE14)					/* vout1_d4.gpio8_4 */
    												
    		>;
    	};
    	
    	uart7_pins: pinmux_uart7_pins {
    		pinctrl-single,pins = <
    			VOUT1_D16 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* vout1_d16.uart7_rxd */
    			//VOUT1_D16 (PIN_OUTPUT | MUX_MODE14)							/* vout1_d16.gpio8_16 */
    			VOUT1_D17 (PIN_OUTPUT | MUX_MODE2)						/* vout1_d17.uart7_txd */		
    			//VOUT1_D17 (PIN_OUTPUT | MUX_MODE14)							/* vout1_d17.gpio8_17 */	
    		>;
    	};
    
    	davinci_mdio_pins_default: pinmux_davinci_mdio_pins_default {
    		pinctrl-single,pins = <
    			/* MDIO */
    				0x190	(	PIN_OUTPUT_PULLUP | MUX_MODE3 )				/* vin2a_d10.mdio_clk */
    				0x194 ( PIN_INPUT_PULLUP | MUX_MODE3 )				/* vin2a_d11.mkio_d */
    		>;
    	};
    
    
    	hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
    		pinctrl-single,pins = <
    			/* this pin is used as a GPIO via mcasp */
    			0x2fc	(PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
    		>;
    	};
    
    	hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
    		pinctrl-single,pins = <
    			0x408	(PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
    			0x40c	(PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
    		>;
    	};
    
    	hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
    		pinctrl-single,pins = <
    			0x408	(PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
    			0x40c	(PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
    		>;
    	};
    
    	dcan1_pins_default: dcan1_pins_default {
    		pinctrl-single,pins = <
    			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* dcan1_tx */
    			0x418   (PULL_UP | MUX_MODE1)		/* wakeup0.dcan1_rx */
    		>;
    	};
    
    	dcan1_pins_sleep: dcan1_pins_sleep {
    		pinctrl-single,pins = <
    			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
    			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
    		>;
    	};
    
    	mmc1_pins_default: pinmux_mmc1_default_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
    			//0x36c (PIN_INPUT | MUX_MODE14)		/* mmc1sdcd.gpio187 */
    		>;
    	};
    
    	mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_hs: pinmux_mmc1_hs_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc2_pins_default: mmc2_pins_default {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc2_pins_hs: pinmux_mmc2_hs_pins {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    };
    
    &dra7_iodelay_core {
    	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
    		pinctrl-single,pins = <
    			0x618 (A_DELAY(572) | G_DELAY(540))	/* CFG_MMC1_CLK_IN */
    			0x624 (A_DELAY(0) | G_DELAY(600))	/* CFG_MMC1_CMD_IN */
    			0x630 (A_DELAY(403) | G_DELAY(120))	/* CFG_MMC1_DAT0_IN */
    			0x63c (A_DELAY(23) | G_DELAY(60))	/* CFG_MMC1_DAT1_IN */
    			0x648 (A_DELAY(25) | G_DELAY(60))	/* CFG_MMC1_DAT2_IN */
    			0x654 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_IN */
    			0x620 (A_DELAY(1525) | G_DELAY(0))	/* CFG_MMC1_CLK_IN */
    			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
    			0x62c (A_DELAY(55) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
    			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
    			0x638 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OUT */
    			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
    			0x644 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OUT */
    			0x64c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
    			0x650 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OUT */
    			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
    			0x65c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OUT */
    		>;
    	};
    
    	mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
    		pinctrl-single,pins = <
    			0x18c (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A19_IN */
    			0x1a4 (A_DELAY(265) | G_DELAY(360))	/* CFG_GPMC_A20_IN */
    			0x1b0 (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A21_IN */
    			0x1bc (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A22_IN */
    			0x1c8 (A_DELAY(287) | G_DELAY(420))	/* CFG_GPMC_A23_IN */
    			0x1d4 (A_DELAY(144) | G_DELAY(240))	/* CFG_GPMC_A24_IN */
    			0x1e0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_IN */
    			0x1ec (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A26_IN */
    			0x1f8 (A_DELAY(120) | G_DELAY(180))	/* CFG_GPMC_A27_IN */
    			0x360 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_IN */
    			0x190 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_OEN */
    			0x194 (A_DELAY(174) | G_DELAY(0))	/* CFG_GPMC_A19_OUT */
    			0x1a8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A20_OEN */
    			0x1ac (A_DELAY(168) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
    			0x1b4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A21_OEN */
    			0x1b8 (A_DELAY(136) | G_DELAY(0))	/* CFG_GPMC_A21_OUT */
    			0x1c0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OEN */
    			0x1c4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OUT */
    			0x1d0 (A_DELAY(879) | G_DELAY(0))	/* CFG_GPMC_A23_OUT */
    			0x1d8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OEN */
    			0x1dc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OUT */
    			0x1e4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OEN */
    			0x1e8 (A_DELAY(34) | G_DELAY(0))	/* CFG_GPMC_A25_OUT */
    			0x1f0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A26_OEN */
    			0x1f4 (A_DELAY(120) | G_DELAY(0))	/* CFG_GPMC_A26_OUT */
    			0x1fc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OEN */
    			0x200 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OUT */
    			0x364 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OEN */
    			0x368 (A_DELAY(11) | G_DELAY(0))	/* CFG_GPMC_CS1_OUT */
    		>;
    	};
    	
    	
    	i2c1_pins_default: pinmux_i2c1_pins {
    		pinctrl-single,pins = <
    			I2C1_SDA (PIN_OUTPUT_PULLUP | MUX_MODE0)  /* i2c1_sda.i2c1_sda */
    			I2C1_SCL (PIN_OUTPUT_PULLUP | MUX_MODE0)  /* i2c1_scl.i2c1_scl */
    		
    		>;
    	};	
    
    	i2c4_pins_default: pinmux_i2c4_pins {
    		pinctrl-single,pins = <
    			MMC1_SDCD (PIN_OUTPUT_PULLUP | MUX_MODE4)  /* mmc1_sdcd.i2c4_sda -> 4 */
    			MMC1_SDWP (PIN_OUTPUT_PULLUP | MUX_MODE4)  /* mmc1_sdwp.i2c4_scl -> 4 */
    
    		>;
    	};
    		
    	mcasp1_pins: mcasp1_pins {
    		pinctrl-single,pins = <
    			MCASP1_ACLKR 	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_0
          MCASP1_FSR    (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_1
    	    MCASP1_AXR3   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_5
    	    MCASP1_AXR4   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_6 
    	    MCASP1_AXR5   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_7 
    	    MCASP1_AXR6   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_8
    	    MCASP1_AXR7   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_9
    		>;
    	};		
    
    	mcasp2_pins: mcasp2_pins {
    		pinctrl-single,pins = <
    			MCASP2_ACLKX  (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated
    			MCASP2_FSX    (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated  
    			MCASP2_AXR0   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated    
    			MCASP2_AXR1   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated    
    			MCASP2_AXR2   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DT_FM3_IBOC_IQ_DI */ 	//gpio6_8			
    			MCASP2_AXR3   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DT_FM3_IBOC_IQ_DQ */ 	//gpio6_9	 
    			MCASP2_AXR5   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DSP_FM_I2C_OUT */ 		//gpio6_7					
    		>;
    	};		
    
    		
    	mcasp3_pins: mcasp3_pins {
    		/* slave */
    		pinctrl-single,pins = <
    #if 0
    			MCASP3_ACLKX	(PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mcasp3_aclkr, mode 1 */	// gpio5_13			B18, 0x324
    			MCASP3_FSX	(PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mcasp3_fsr, mode 1 */	// gpio5_14			F15, 0x328
    #else
    			MCASP3_ACLKX	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mcasp3_aclkr, mode 14 gpio */// gpio5_13			B18, 0x324
    			MCASP3_FSX	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mcasp3_fsr, mode 14 gpio */	// gpio5_14			F15, 0x328
    #endif
    
    #if 1
    			MCASP3_AXR0	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mcasp3_axr0, mode 0 */	// decidated			B19, 0x32C
    			MCASP3_AXR1	(PIN_OUTPUT_PULLUP | MUX_MODE0)	/* mcasp3_axr1, mode 0 */	// decidated			C17, 0x330
    #else
    //AB MCASP3 loopback test
    			MCASP3_AXR0	(PIN_OUTPUT_PULLDOWN | MUX_MODE15)	/* mcasp3_axr0, off mode */	// decidated			B19, 0x32C
    			MCASP3_AXR1	(PIN_OUTPUT_PULLDOWN | MUX_MODE15)	/* mcasp3_axr1, off mode */	// decidated			C17, 0x330
    #endif
    		>;
    	};		
    	
    	mcasp4_pins: mcasp4_pins {
    		pinctrl-single,pins = <
    			MCASP4_ACLKX 	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// decidated
    			MCASP4_FSX  	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */ 	// decidated  
          MCASP4_AXR0   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// decidated 
    		>;
    	};			
    
    		
    };
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	tps659038: tps659038@58 {
    		compatible = "ti,tps659038";
    		reg = <0x58>;
    
    		tps659038_pmic {
    			compatible = "ti,tps659038-pmic";
    
    			regulators {
    			 /*
    				smps123_reg: smps123 {
    					// VDD_MPU
    					regulator-name = "smps123";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    			  */
    
    				smps12_reg: smps12 {
    					/* VDD_MPU */
    					regulator-name = "smps12";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    				
    				smps3_reg: smps3 {
    					/* VDD_DDR */
    					regulator-name = "smps3";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps45_reg: smps45 {
    					/* VDD_DSPEVE */
    					regulator-name = "smps45";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1150000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps6_reg: smps6 {
    					/* VDD_GPU - over VDD_SMPS6 */
    					regulator-name = "smps6";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps7_reg: smps7 {
    					/* CORE_VDD */
    					regulator-name = "smps7";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1060000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps8_reg: smps8 {
    					/* VDD_IVAHD */
    					regulator-name = "smps8";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps9_reg: smps9 {
    					/* VDDS1V8 */
    					regulator-name = "smps9";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo1_reg: ldo1 {
    					/* LDO1_OUT --> SDIO  */
    					regulator-name = "ldo1";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo2_reg: ldo2 {
    					/* VDD_RTCIO */
    					/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
    					regulator-name = "ldo2";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo3_reg: ldo3 {
    					/* VDDA_1V8_PHY */
    					regulator-name = "ldo3";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo9_reg: ldo9 {
    					/* VDD_RTC */
    					regulator-name = "ldo9";
    					regulator-min-microvolt = <1050000>;
    					regulator-max-microvolt = <1050000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldoln_reg: ldoln {
    					/* VDDA_1V8_PLL */
    					regulator-name = "ldoln";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldousb_reg: ldousb {
    					/* VDDA_3V_USB: VDDA_USBHS33 */
    					regulator-name = "ldousb";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				/* REGEN1 is unused */
    				regen1: regen1 {
    					/* Needed for PMIC internal resources */
    					regulator-name = "regen1";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    
    				regen2: regen2 {
    					/* Needed for PMIC internal resources */
    					regulator-name = "regen2";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				/* REGEN3 is unused */
    
    				sysen1: sysen1 {
    					/* PMIC_REGEN_3V3 */
    					regulator-name = "sysen1";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				sysen2: sysen2 {
    					/* PMIC_REGEN_DDR */
    					regulator-name = "sysen2";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    			};
    		};
    	};
    
    	pcf_lcd: gpio@20 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x20>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	pcf_gpio_21: gpio@21 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x21>;
    		lines-initial-states = <0x1408>;
    		gpio-controller;
    		#gpio-cells = <2>;
    		interrupt-parent = <&gpio6>;
    		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
    		interrupt-controller;
    		#interrupt-cells = <2>;
    	};
    
    
    	tlv320aic3106: tlv320aic3106@18 {
    		status = "disabled";
    		compatible = "ti,tlv320aic3106";
    		reg = <0x18>;
    		adc-settle-ms = <40>;
    		ai3x-micbias-vg = <1>;		/* 2.0V */
    		//status = "okay";
    
    		/* Regulators */
    		AVDD-supply = <&evm_3v3_sw>;
    		IOVDD-supply = <&evm_3v3_sw>;
    		DRVDD-supply = <&evm_3v3_sw>;
    		DVDD-supply = <&aic_dvdd>;
    	};
    };
    
    i2c_p3_exp: &i2c2 {
    	status = "disabled";
    	clock-frequency = <400000>;
    
    	pcf_hdmi: gpio@26 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x26>;
    		lines-initial-states = <0xffeb>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	ov10633@37 {
    		compatible = "ovti,ov10633";
    		reg = <0x37>;
    		status = "disabled";
    		mux-gpios = <&pcf_hdmi 3	GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
    		port {
    			onboardLI: endpoint {
    				remote-endpoint = <&vin1a>;
    				hsync-active = <1>;
    				vsync-active = <1>;
    				pclk-sample = <0>;
    			};
    		};
    	};
    };
    
    &i2c2 {
    	status = "okay";
    	clock-frequency = <400000>;
    };
    
    &i2c3 {
    	status = "disabled";
    	clock-frequency = <3400000>;
    };
    
    &i2c4 {
    	status = "disabled";
    	clock-frequency = <400000>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&i2c4_pins_default>;	
    };
    
    
    &i2c5 {
    	status = "okay";
    	clock-frequency = <400000>;
    };
    
    &mcspi1 {
    	//status = "okay";
    	status = "disabled";
    };
    
    &mcspi2 {
    	//status = "okay";
    	status = "disabled";
    };
    
    &uart1 {
    	status = "okay";
    	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
    			       &dra7_pmx_core 0x3e0>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart1_pins>;
    };
    
    &uart2 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart2_pins>;		
    };
    
    /*
    * &uart3 {
    *	status = "okay";
    *	gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
    * };
    */
    
    &uart3 {
    	status = "okay";
    	//gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart3_pins>;
    };
    
    &uart5 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart5_pins>;
    };
    
    &uart7 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart7_pins>;
    };
    
    
    &mmc1 {
    	status = "okay";
    	pbias-supply = <&pbias_mmc_reg>;
    	vmmc-supply = <&evm_3v3_sd>;
    	vmmc_aux-supply = <&ldo1_reg>;
    	bus-width = <4>;
    	/*
    	 * SDCD signal is not being used here - using the fact that GPIO mode
    	 * is always hardwired.
    	 */
    	/* cd-gpios = <&gpio6 27 0>; */
    	ti,non-removable;
    	pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
    	pinctrl-0 = <&mmc1_pins_default>;
    	pinctrl-1 = <&mmc1_pins_hs>;
    	pinctrl-2 = <&mmc1_pins_sdr12>;
    	pinctrl-3 = <&mmc1_pins_sdr25>;
    	pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
    	sd-uhs-ddr50;
    	sd-uhs-sdr25;
    	sd-uhs-sdr12;
    };
    
    
    &mmc2 {
    	status = "disabled";
    	//status = "okay";
    	vmmc-supply = <&evm_3v3_sw>;
    	bus-width = <8>;
    	pinctrl-names = "default", "hs", "ddr_3_3v";
    	pinctrl-0 = <&mmc2_pins_default>;
    	pinctrl-1 = <&mmc2_pins_hs>;
    	pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
    	mmc-ddr-1_8v;
    };
    
    &mmc4 {
    	//status = "okay";
    	status = "disabled";
    	vmmc-supply = <&vmmcwl_fixed>;
    	bus-width = <4>;
    	cap-power-off-card;
    	keep-power-in-suspend;
    	ti,non-removable;
    
    	#address-cells = <1>;
    	#size-cells = <0>;
    	wlcore: wlcore@0 {
    		compatible = "ti,wlcore";
    		reg = <2>;
    		interrupt-parent = <&gpio5>;
    		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    	};
    };
    
    &cpu0 {
    	cpu0-voltdm = <&voltdm_mpu>;
    	voltage-tolerance = <1>;
    };
    
    &voltdm_mpu {
    	// OTP 82
    	//vdd-supply = <&smps123_reg>;
    	
    	// OTP60
    	vdd-supply = <&smps12_reg>;	
    };
    
    &voltdm_dspeve {
    	vdd-supply = <&smps45_reg>;
    };
    
    &voltdm_gpu {
    	vdd-supply = <&smps6_reg>;
    };
    
    &voltdm_ivahd {
    	vdd-supply = <&smps8_reg>;
    };
    
    &voltdm_core {
    	vdd-supply = <&smps7_reg>;
    };
    
    &qspi {
    	status = "okay";
    
    	spi-max-frequency = <48000000>;
    	m25p80@0 {
    		status = "disabled";
    		compatible = "s25fl256s1";
    		spi-max-frequency = <48000000>;
    		reg = <0>;
    		spi-tx-bus-width = <1>;
    		spi-rx-bus-width = <4>;
    		spi-cpol;
    		spi-cpha;
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		/* MTD partition table.
    		 * The ROM checks the first four physical blocks
    		 * for a valid file to boot and the flash here is
    		 * 64KiB block size.
    		 */
    		partition@0 {
    			label = "QSPI.SPL";
    			reg = <0x00000000 0x000010000>;
    		};
    		partition@1 {
    			label = "QSPI.SPL.backup1";
    			reg = <0x00010000 0x00010000>;
    		};
    		partition@2 {
    			label = "QSPI.SPL.backup2";
    			reg = <0x00020000 0x00010000>;
    		};
    		partition@3 {
    			label = "QSPI.SPL.backup3";
    			reg = <0x00030000 0x00010000>;
    		};
    		partition@4 {
    			label = "QSPI.u-boot";
    			reg = <0x00040000 0x00100000>;
    		};
    		partition@5 {
    			label = "QSPI.u-boot-spl-os";
    			reg = <0x00140000 0x00080000>;
    		};
    		partition@6 {
    			label = "QSPI.u-boot-env";
    			reg = <0x001c0000 0x00010000>;
    		};
    		partition@7 {
    			label = "QSPI.u-boot-env.backup1";
    			reg = <0x001d0000 0x0010000>;
    		};
    		partition@8 {
    			label = "QSPI.kernel";
    			reg = <0x001e0000 0x0800000>;
    		};
    		partition@9 {
    			label = "QSPI.file-system";
    			reg = <0x009e0000 0x01620000>;
    		};
    	};
    };
    
    &omap_dwc3_1 {
    		status = "ok";
    	extcon = <&extcon_usb1>;
    };
    
    &omap_dwc3_2 {
    		status = "ok";
    	extcon = <&extcon_usb2>;
    };
    
    &usb1 {
    dr_mode = "otg" ;
    };
    
    &usb2 {
    dr_mode = "otg" ;
    };
    
    
    &mac {
    	pinctrl-names = "default";
        pinctrl-0 = <&cpsw_default>;
    	status = "okay";
    	dual_emac;
    	ti,no-idle;
    };
    
    &davinci_mdio {
    	pinctrl-names = "default";
    	pinctrl-0 = <&davinci_mdio_pins_default>;
    };
    
    &cpsw_emac0 {
    	phy_id = <&davinci_mdio>, <0>;
    	phy-mode = "rgmii";
    	dual_emac_res_vlan = <1>;
    };
    
    &cpsw_emac1 {
    	phy_id = <&davinci_mdio>, <21>;
    	phy-mode = "rgmii";
    	dual_emac_res_vlan = <2>;
    };
    
    
    &elm {
    	status = "okay";
    };
    
    &gpmc {
    	status = "disabled";
    	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
    	nand@0,0 {
    		reg = <0 0 4>;		/* device IO registers */
    		ti,nand-ecc-opt = "bch8";
    		ti,elm-id = <&elm>;
    		nand-bus-width = <16>;
    		gpmc,device-width = <2>;
    		gpmc,sync-clk-ps = <0>;
    		gpmc,cs-on-ns = <0>;
    		gpmc,cs-rd-off-ns = <80>;
    		gpmc,cs-wr-off-ns = <80>;
    		gpmc,adv-on-ns = <0>;
    		gpmc,adv-rd-off-ns = <60>;
    		gpmc,adv-wr-off-ns = <60>;
    		gpmc,we-on-ns = <10>;
    		gpmc,we-off-ns = <50>;
    		gpmc,oe-on-ns = <4>;
    		gpmc,oe-off-ns = <40>;
    		gpmc,access-ns = <40>;
    		gpmc,wr-access-ns = <80>;
    		gpmc,rd-cycle-ns = <80>;
    		gpmc,wr-cycle-ns = <80>;
    		gpmc,bus-turnaround-ns = <0>;
    		gpmc,cycle2cycle-delay-ns = <0>;
    		gpmc,clk-activation-ns = <0>;
    		gpmc,wait-monitoring-ns = <0>;
    		gpmc,wr-data-mux-bus-ns = <0>;
    		/* MTD partition table */
    		/* All SPL-* partitions are sized to minimal length
    		 * which can be independently programmable. For
    		 * NAND flash this is equal to size of erase-block */
    		#address-cells = <1>;
    		#size-cells = <1>;
    		partition@0 {
    			label = "NAND.SPL";
    			reg = <0x00000000 0x000020000>;
    		};
    		partition@1 {
    			label = "NAND.SPL.backup1";
    			reg = <0x00020000 0x00020000>;
    		};
    		partition@2 {
    			label = "NAND.SPL.backup2";
    			reg = <0x00040000 0x00020000>;
    		};
    		partition@3 {
    			label = "NAND.SPL.backup3";
    			reg = <0x00060000 0x00020000>;
    		};
    		partition@4 {
    			label = "NAND.u-boot-spl-os";
    			reg = <0x00080000 0x00040000>;
    		};
    		partition@5 {
    			label = "NAND.u-boot";
    			reg = <0x000c0000 0x00100000>;
    		};
    		partition@6 {
    			label = "NAND.u-boot-env";
    			reg = <0x001c0000 0x00020000>;
    		};
    		partition@7 {
    			label = "NAND.u-boot-env.backup1";
    			reg = <0x001e0000 0x00020000>;
    		};
    		partition@8 {
    			label = "NAND.kernel";
    			reg = <0x00200000 0x00800000>;
    		};
    		partition@9 {
    			label = "NAND.file-system";
    			reg = <0x00a00000 0x0f600000>;
    		};
    	};
    };
    
    &gpio2 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*	
    	gpio2_0 {
    		gpio-hog;
    		gpios = < 0 0 >;
    		output-high;
    		line-name = "MD_12VPA_EN";
    	};
    
    	gpio2_1 {
    		gpio-hog;
    		gpios = < 1 0 >;
    		output-high;
    		line-name = "MD_12VPB_EN";
    	};
    	
    	gpio2_2 {
    		gpio-hog;
    		gpios = < 2 0 >;
    		output-high;
    		line-name = "SOC_POWER_ON";
    	};
    */	
    };
    
    &gpio3 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*
    	gpio3_6 {
    		gpio-hog;
    		gpios = < 6 0 >;
    		output-high;
    		line-name = "SOC_RESET_IN";
    	};
    	
    	gpio3_29 {
    		gpio-hog;
    		gpios = < 29 0 >;
    		output-high;
    		line-name = "AB_DEBUG_MUX_AB_USB";
    	};
    */	
    };
    
    &gpio7 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*	
    	gpio7_0 {
    		gpio-hog;
    		gpios = < 0 0 >;
    		output-high;
    		line-name = "BOOT_MODE0";	
    	};	
    
    	gpio7_1 {
    		gpio-hog;
    		gpios = < 1 0 >;
    		output-low;
    		line-name = "BOOT_MODE1";
    	};
    */	
    };
    
    &gpio8 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*
    	gpio8_9 {
    		gpio-hog;
    		gpios = < 9 0 >;
    		output-high;
    		line-name = "FPGA_RST_N";
    	};
    */
    };
    
    &dss {
    	//status = "ok";
    	status = "disabled";
    	vdda_video-supply = <&ldoln_reg>;
    };
    
    &hdmi {
    	//status = "ok";
    	status = "disabled";
    	vdda-supply = <&ldo3_reg>;
    
    	port {
    		hdmi_out: endpoint {
    			remote-endpoint = <&tpd12s015_in>;
    		};
    	};
    };
    
    &dcan1 {
    	//status = "ok";
    	status = "disabled";
    	pinctrl-names = "default", "sleep";
    	pinctrl-0 = <&dcan1_pins_default>;
    	pinctrl-1 = <&dcan1_pins_sleep>;
    };
    
    &mailbox5 {
    	status = "okay";
    	mbox_ipu1_legacy: mbox_ipu1_legacy {
    		status = "okay";
    	};
    	mbox_dsp1_legacy: mbox_dsp1_legacy {
    		status = "okay";
    	};
    };
    
    &mailbox6 {
    	status = "okay";
    	mbox_ipu2_legacy: mbox_ipu2_legacy {
    		status = "okay";
    	};
    	mbox_dsp2_legacy: mbox_dsp2_legacy {
    		status = "okay";
    	};
    };
    
    &mmu0_dsp1 {
    	status = "okay";
    };
    
    &mmu1_dsp1 {
    	status = "okay";
    };
    
    &mmu0_dsp2 {
    	status = "okay";
    };
    
    &mmu1_dsp2 {
    	status = "okay";
    };
    
    &mmu_ipu1 {
    	status = "okay";
    };
    
    &mmu_ipu2 {
    	status = "okay";
    };
    
    &ipu2 {
    	status = "okay";
    	memory-region = <&ipu2_cma_pool>;
    	mboxes = <&mailbox6 &mbox_ipu2_legacy>;
    	timers = <&timer3>;
    	watchdog-timers = <&timer4>, <&timer9>;
    };
    
    &ipu1 {
    	status = "okay";
    	memory-region = <&ipu1_cma_pool>;
    	mboxes = <&mailbox5 &mbox_ipu1_legacy>;
    	timers = <&timer11>;
    	watchdog-timers = <&timer7>, <&timer8>;
    };
    
    &dsp1 {
    	status = "okay";
    	memory-region = <&dsp1_cma_pool>;
    	mboxes = <&mailbox5 &mbox_dsp1_legacy>;
    	timers = <&timer5>;
    	watchdog-timers = <&timer10>;
    };
    
    &dsp2 {
    	status = "okay";
    	memory-region = <&dsp2_cma_pool>;
    	mboxes = <&mailbox6 &mbox_dsp2_legacy>;
    	timers = <&timer6>;
    };
    
    &atl {
    	status = "okay";
    
    	atl2 {
    		bws = <DRA7_ATL_WS_MCASP2_FSX>;
    		aws = <DRA7_ATL_WS_MCASP3_FSX>;
    	};
    };
    
    // LOUIS ADD
    &mcasp1 {
    
    	//pinctrl-names = "default";
    	//pinctrl-0 = <&mcasp1_pins>;
    		
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 16 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		0 0 0 1  1 1 2 2
    		0 0 0 0  0 0 0 0
    	>;
    	tx-num-evt = <8>;			// fifo event level
    	rx-num-evt = <8>;
    };
    
    // LOUIS ADD
    &mcasp2 {
    
    	//pinctrl-names = "default";
    	//pinctrl-0 = <&mcasp2_pins>;
    		
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 16 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 2 1  0 1 0 0
    		0 0 0 0  0 0 0 0
    	>;
    	tx-num-evt = <8>;			// fifo event level
    	rx-num-evt = <8>;
    };
    
    &mcasp3 {
    	#sound-dai-cells = <0>;
    	fck_parent = "atl_clkin2_ck";
    
    #if 1
    //2017/07/12 prepare firmware to Production Line TDM in GPIO mode first
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcasp3_pins>;
    
    	status = "okay";
    #else
    	status = "disabled";
    #endif
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    // LOUIS ADD
    &mcasp4 {
    
    	//pinctrl-names = "default";
    	//pinctrl-0 = <&mcasp4_pins>;
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		1 0 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    
    &mcasp7 {
    	#sound-dai-cells = <0>;
    
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;  /* MCASP_IIS_MODE */
    	tdm-slots = <4>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    &mcasp8 {
    	/* not used for audio. only the AXR2 pin is used as GPIO */
    	status = "disabled";
    };
    
    &usb2_phy1 {
    	phy-supply = <&ldousb_reg>;
    };
    
    &usb2_phy2 {
    	phy-supply = <&ldousb_reg>;
    };
    
    &vip1 {
    	status = "okay";
    };
    
    video_in: &vin1a {
    	//status = "okay";
    	status = "disabled";
    	endpoint@0 {
    		slave-mode;
    		remote-endpoint = <&onboardLI>;
    	};
    };
    
    #include "dra7xx-jamr3.dtsi"
    
    //
    //&tvp_5158{
    //	mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>,	/*CAM_FPD_MUX_S0*/
    //			<&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>;	/*SEL_TVP_FPD*/
    //};
    

    BRs

    Louis

  • Could you set the McASP3 pinmux as follows:
    * McASP3 ACLKX -> output, pulldown
    * McASP3 FSX -> output, pulldown
    * McASP3 AXR0 -> input
    * McASP3 AXR1 -> output, pulldown

    The other device-tree settings look ok.

    Make sure that you also run arecord (with the same parameters, i.e. sample rate, bits/sample, channels) in parallel with aplay to capture the looped back data.
  • Hi Misael,

    1. Carrier Board can work well with loopback test, thanks for your help.

    2. Now I face a issue with Carrier Board Adapt Board connection test, that is, Carrier Board be I2S slave, Adapt Board be I2S host.

    * Carrier Board MCASP3_AXR0 be input, Adapt Board MCASP3_AXR0 be output.

    * Carrier Board MCASP3_AXR1 be output, Adapt Board MCASP3_AXR1 be input.

    * Carrier Board clock with MCASP3_CLKR and MCASP3_FSR, Adapt Board clock with MCASP3_ACLKX and MCASP3_FSX

    Both Adapt Board and Carrier Board can capture audio from each other, but the file captured by "arecord" isn't correct.

    3. The attached file shows DTS settings

    Carrier_Board_dra7-evm.dts.txt
    /*
     * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    /dts-v1/;
    
    #include "dra74x.dtsi"
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clk/ti-dra7-atl.h>
    #include <dt-bindings/pinmux/mux_dra7xx.h>
    
    / {
    	model = "TI DRA742 Louis 20170731 10:10";
    	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
    	
    	version = "20161109" ;
    	
    	memory {
    		device_type = "memory";
    		//reg = <0x80000000 0x60000000>; /* 1536 MB */							
    		//reg = <0x80000000 0x80000000>; /* 2048 MB */
    		reg = <0x80000000 0x20000000>; /* 512 MB */
    	};
    
    
    	leds {
    		pinctrl-names = "default";
    		pinctrl-0 = <&user_leds_default>;
    
    		compatible = "gpio-leds";
    
    		led@1 {
    			label = "FPGA_EN";
    			gpios = <&gpio8 23 GPIO_ACTIVE_HIGH>;
    			linux,default-trigger = "none";
    			default-state = "on";
    		};
    	};
    
    	reserved_mem: reserved-memory {
    		#address-cells = <1>;
    		#size-cells = <1>;
    		ranges;
    
    		ipu2_cma_pool: ipu2_cma@95800000 {
    			compatible = "shared-dma-pool";
    			reg = <0x95800000 0x3800000>;
    			reusable;
    			status = "okay";
    		};
    
    		dsp1_cma_pool: dsp1_cma@99000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x99000000 0x4000000>;
    			reusable;
    			status = "okay";
    		};
    
    		ipu1_cma_pool: ipu1_cma@9d000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x9d000000 0x2000000>;
    			reusable;
    			status = "okay";
    		};
    
    		dsp2_cma_pool: dsp2_cma@9f000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x9f000000 0x800000>;
    			reusable;
    			status = "okay";
    		};
    	};
    
    	extcon_usb1: extcon_usb1 {
    		status = "ok";
    		compatible = "linux,extcon-usb-gpio";
    		//id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
    		id-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
    	};
    
    	extcon_usb2: extcon_usb2 {
    		status = "ok";
    		compatible = "linux,extcon-usb-gpio";
    		//id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
    		id-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
    	};
    
    	evm_3v3_sd: fixedregulator-sd {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sd";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	evm_3v3_sw: fixedregulator-evm_3v3_sw {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sw";
    		vin-supply = <&sysen1>;
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	aic_dvdd: fixedregulator-aic_dvdd {
    		/* TPS77018DBVT */
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd";
    		vin-supply = <&evm_3v3_sw>;
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    	};
    
    	vmmcwl_fixed: fixedregulator-mmcwl {
    		compatible = "regulator-fixed";
    		regulator-name = "vmmcwl_fixed";
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    		//gpio = <&gpio5 8 0>;	/* gpio5_8 */
    		startup-delay-us = <70000>;
    		enable-active-high;
    	};
    
    /*
    	kim {
    		compatible = "kim";
    		nshutdown_gpio = <132>;
    		dev_name = "/dev/ttyS2";
    		flow_cntrl = <1>;
    		baud_rate = <3686400>;
    	};
    
    	btwilink {
    		compatible = "btwilink";
    	};
    */
    	vtt_fixed: fixedregulator-vtt {
    		compatible = "regulator-fixed";
    		regulator-name = "vtt_fixed";
    		regulator-min-microvolt = <1350000>;
    		regulator-max-microvolt = <1350000>;
    		regulator-always-on;
    		regulator-boot-on;
    		enable-active-high;
    		vin-supply = <&sysen2>;
    		//gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
    	};
    
    	aliases {
    		display0 = &hdmi0;
    		sound0 = &snd0;
    		sound1 = &hdmi;
    	};
    
    	hdmi0: connector@1 {
    		compatible = "hdmi-connector";
    		label = "hdmi";
    
    		type = "a";
    
    		port {
    			hdmi_connector_in: endpoint {
    				remote-endpoint = <&tpd12s015_out>;
    			};
    		};
    	};
    
    	tpd12s015: encoder@1 {
    		compatible = "ti,dra7evm-tpd12s015";
    		status = "disabled";
    
    		pinctrl-names = "i2c", "ddc";
    		pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
    		pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
    
    		ddc-i2c-bus = <&i2c2>;
    		mcasp-gpio = <&mcasp8>;
    
    		gpios = <&pcf_hdmi 4 0>,	/* P4, CT CP HPD */
    			<&pcf_hdmi 5 0>,	/* P5, LS OE */
    			<&gpio7 12 0>;	/* gpio7_12/sp1_cs2, HPD */
    
    		ports {
    			#address-cells = <1>;
    			#size-cells = <0>;
    
    			port@0 {
    				reg = <0>;
    
    				tpd12s015_in: endpoint@0 {
    					remote-endpoint = <&hdmi_out>;
    				};
    			};
    
    			port@1 {
    				reg = <1>;
    
    				tpd12s015_out: endpoint@0 {
    					remote-endpoint = <&hdmi_connector_in>;
    				};
    			};
    		};
    	};
    
        ocp {
            gpu: gpu@0x56000000 {
                gpu0-voltdm = <&voltdm_gpu>;
            };
        };
    
    	btsco: btsco@0 {
    		#sound-dai-cells = <0>;
    		status = "okay";
    		compatible = "linux,bt-sco-audio";
    	};
    
    
            snd0: sound@0 {
                    compatible = "simple-audio-card";
                    simple-audio-card,name = "DRA7xx-EVM";
    #if 0
    		/* we do not have codec */
    		simple-audio-card,mclk-fs = <256>;
    #endif
                    simple-audio-card,widgets =
                            "Headphone", "Headphone Jack",
                            "Line", "Line Out",
                            "Microphone", "Mic Jack",
                            "Line", "Line In";
                    simple-audio-card,routing =
                            "Headphone Jack",       "HPLOUT",
                            "Headphone Jack",       "HPROUT",
                            "Line Out",             "LLOUT",
                            "Line Out",             "RLOUT",
                            "MIC3L",                "Mic Jack",
                            "MIC3R",                "Mic Jack",
                            "Mic Jack",             "Mic Bias",
                            "LINE1L",               "Line In",
                            "LINE1R",               "Line In";
    		status = "okay";
    
    #if 1
    		simple-audio-card,dai-link@0 {
    			format = "i2s";
    			bitclock-master = <&sound0_master>;
    			frame-master = <&sound0_master>;
    			bitclock-inversion;
    
    			sound0_master: cpu {
    				sound-dai = <&mcasp3>;
    				system-clock-frequency = <8192000>;
    			};
    
    			codec {
    				sound-dai = <&btsco>;
    			};
    		};
    #else
                    simple-audio-card,format = "i2s";
                    simple-audio-card,bitclock-master = <&sound0_master>;
                    simple-audio-card,frame-master = <&sound0_master>;
                    simple-audio-card,bitclock-inversion;
    
                    sound0_master: simple-audio-card,cpu {
                            sound-dai = <&mcasp3>;
                            system-clock-frequency = <11289600>;
                    };  
    
                    simple-audio-card,codec {
                            sound-dai = <&btsco>;
                            clocks = <&atl_clkin2_ck>;
                    };
    #endif
            };
    };
    
    &dra7_pmx_core {
    
        // 20161109 For CB ver.F
    	cpsw_default: cpsw_default {
    		pinctrl-single,pins = <
    			// Slave 1 
    			
    			0x250 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_tclk.rgmii0_tclk W9 
    			0x254 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_tctl.rgmii0_tctl V9 
    			0x258 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td3.rgmii0_td3  V7 
    			0x25c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td2.rgmii0_td2  U7
    			0x260 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td1.rgmii0_td1 V6 
    			0x264 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td0.rgmii0_td0 U6 
    			0x268 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rmii0_rclk.rmii0_rclk U5 
    			0x26c (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rctl.rgmii0_rctl V5 
    			0x270 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd3.rgmii0_rd3 V4 
    			0x274 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd2.rgmii0_rd2 V3 
    			0x278 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd1.rgmii0_rd1 Y2 
    			0x27c (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd0.rgmii0_rd0 W2 
    			
    			
    			// Slave 2 
    			0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d12.rgmii1_tclk D5 
    			0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d13.rgmii1_tctl C2 
    			0x1a0 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d14.rgmii1_td3 C3 
    			0x1a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d15.rgmii1_td2 C4 
    			0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d16.rgmii1_td1 B2 
    			0x1ac (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d17.rgmii1_td0 D6 
    			0x1b0 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d18.rgmii1_rclk C5 
    			0x1b4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d19.rgmii1_rctl A3 
    			0x1b8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d20.rgmii1_rd3 B3 
    			0x1bc (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d21.rgmii1_rd2 B4 
    			0x1c0 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d22.rgmii1_rd1 B5 
    			0x1c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d23.rgmii1_rd0 A4
    		>;
    	};
    
    	
    	uart1_pins: pinmux_uart1_pins {
    		pinctrl-single,pins = <		
    
    			/* audio mcasp3 with loopback test */
    			MCASP3_AXR0	(PIN_INPUT           | MUX_MODE0)	/* mcasp3_axr0, mode 0 */	// decidated	B19, 0x32C
    			MCASP3_AXR1	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr1, mode 0 */	// decidated	C17, 0x330
    			MCASP3_ACLKX	(PIN_INPUT | MUX_MODE1)			/* mcasp3_aclkr, */		//		B18, 0x324
    			MCASP3_FSX	(PIN_INPUT | MUX_MODE1)			/* mcasp3_fsr, */		//		F15, 0x328
    
    			UART1_RXD		(WAKEUP_EN | PIN_INPUT | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
    			UART1_TXD		(PIN_OUTPUT | MUX_MODE0)		/* uart1_txd.uart1_txd */		
    			UART1_CTSN	(PIN_OUTPUT | MUX_MODE0)			/* uart1_ctsn.uart1_ctsn */
    			UART1_RTSN	(PIN_INPUT | MUX_MODE0) 			/* uart1_rtsn.uart1_rtsn */
    
    			/* Can not do pin defines in I2C section */
    			/* Move all the I2C pin defines here */
    			// I2C1 controls
    			VIN2A_D0	(PIN_INPUT | MUX_MODE14)				 /* vin2a_d0.gpio4_1 */
    			VIN2A_D1	(PIN_INPUT | MUX_MODE14)				 /* vin2a_d1.gpio4_2 */	
    			// I2C4 controls
    			VIN1A_D7	(PIN_INPUT | MUX_MODE14)				 /* vin1a_d7.gpio3_11 */
    			VIN1A_D8	(PIN_INPUT | MUX_MODE14)				 /* vin1a_d8.gpio3_12 */
    			
    			//I2C4 PIN defines		
    			//MMC1_SDCD (PIN_INPUT | MUX_MODE4)  /* mmc1_sdcd.i2c4_sda -> 4 */
    			//MMC1_SDWP (PIN_INPUT | MUX_MODE4)  /* mmc1_sdwp.i2c4_scl -> 4 */
    			//I2C4 as GPIO		
    			MMC1_SDCD (PIN_INPUT | MUX_MODE14)  /* mmc1_sdcd.gpio?_?? */
    			MMC1_SDWP (PIN_INPUT | MUX_MODE14)  /* mmc1_sdwp.gpio?_?? */	
    
    			//I2C5 as GPIO for 7-segment display, Carrier Board hardware ver #F use i2c5
    			GPMC_A4 (PIN_INPUT | MUX_MODE7) /* gpmc_a4.i2c5_scl -> 7 */
    			GPMC_A5 (PIN_INPUT | MUX_MODE7) /* gpmc_a5.i2c5_sda -> 7 */
    
    			// POWINGING_SEQUENCE
    			// MD_12VPA_EN
    			GPMC_A10		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a10.gpio2_0 */
    			// MD_12VPB_EN
    			GPMC_A11		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a11.gpio2_1 */
    			// SOC_POWER_ON
    			GPMC_A12		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a12.gpio2_2 */
    #if 1       // 20161109 For CB ver.F			
    			// AB_VERSION
    			GPMC_A13		(PIN_INPUT | MUX_MODE14)		/* gpmc_a13.gpio2_3 */
    			GPMC_A14		(PIN_INPUT | MUX_MODE14)		/* gpmc_a14.gpio2_4 */
    			GPMC_A15		(PIN_INPUT | MUX_MODE14)		/* gpmc_a15.gpio2_5 */
    			GPMC_A16		(PIN_INPUT | MUX_MODE14)		/* gpmc_a16.gpio2_6 */
    
    			// CB_VERSION
    			GPMC_A13		(PIN_INPUT | MUX_MODE14)		/* gpmc_a13.gpio2_7 */
    			GPMC_A14		(PIN_INPUT | MUX_MODE14)		/* gpmc_a14.gpio2_8 */
    			GPMC_A15		(PIN_INPUT | MUX_MODE14)		/* gpmc_a15.gpio2_9 */
    			GPMC_A16		(PIN_INPUT | MUX_MODE14)		/* gpmc_a16.gpio2_10 */
    #endif
    							
    			// SOC_REST_EN
    			VIN1A_D2		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d2.gpio3_6 */
    
    			// BOOT MODE				
    			MMC3_DAT1		(PIN_INPUT | MUX_MODE14)		/* mmc3_dat1.gpio7_0 */
    			MMC3_DAT2		(PIN_INPUT | MUX_MODE14)		/* mmc3_dat2.gpio7_1 */	
    	
    			// DEBUG MESSAGE MUX CONTROL
    		  	VIN2A_DE0		(PIN_OUTPUT | MUX_MODE14)		/* vin2a_de0.gpio3_29  ==> 0x4A00_3558  ==> 0x1558 ==> 0x158 */	 
    
    		 	// LGA_SYSBOOT_1, _2, _3, _5
    		 	VIN1A_D21		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d21.gpio3_25	*/
    		 	VIN1A_D22		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d22.gpio3_26 */
    		 	USB2_DRVVBUS		(PIN_OUTPUT | MUX_MODE14)		/* usb2_drvvbus.gpio6_13 */
    		 	//GPMC_A25		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a25.gpio2_15 */
    		 	
    		 	// SATA_PATH_SELECT
    		 	GPMC_A6			(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a6.gpio1_28 */
                            // SATA_RST_N
                            GPIO6_14		(PIN_OUTPUT | MUX_MODE14)
    
    
    			// Carrier Board control Adapt Board INA226 chip x 5, only for iMX6, use i2c2, gpio5_2 & gpio5_3 both need in gpio input
    			MCASP1_AXR0 (PIN_INPUT | MUX_MODE14)	/* mcasp1_axr0.gpio5_2 -> 10 */
    			MCASP1_AXR1 (PIN_INPUT | MUX_MODE14)	/* mcasp1_axr1.gpio5_3 -> 10 */
    			
    			0x408	(PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
    			0x40c	(PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
    
    //=================================================================================							
    		>;
    	};
    	
    	user_leds_default: user_leds_default {
    		pinctrl-single,pins = <
    			0x238 (PIN_OUTPUT | MUX_MODE14)	/* vout1_d23.gpio8_23 A10 FPGA_EN */	
    		>;
    	};
    	
    	uart2_pins: pinmux_uart2_pins {
    		pinctrl-single,pins = <
    			UART2_RXD		(WAKEUP_EN | PIN_INPUT | MUX_MODE4)	/* uart2_rxd.uart2_rxd */
    			UART2_TXD		(PIN_OUTPUT | MUX_MODE4)		/* uart2_txd.uart2_txd */		
    		>;
    	};	
    	
    	uart3_pins: pinmux_uart3_pins {
    		pinctrl-single,pins = <
    			0x3f8 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* uart2_ctsn.uart3_rxd */
    			0x3fc (PIN_OUTPUT | MUX_MODE1)			/* uart2_rtsn.uart3_txd */			
    		>;
    	};
    
    //   Socket board
    
    //	uart3_pins: pinmux_uart3_pins {
    //		pinctrl-single,pins = <
    //			0x34c (PIN_INPUT_PULLUP | PIN_INPUT | MUX_MODE4)	/* mcasp5_axr0.uart3_rxd */
    //			0x350 (PIN_OUTPUT | MUX_MODE4)	/* mcasp5_axr1.uart3_txd */			
    //		>;
    //	};
    
    	uart5_pins: pinmux_uart5_pins {
    		pinctrl-single,pins = <
    			VOUT1_D0 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* vout1_d0.uart5_rxd */
    			VOUT1_D1 (PIN_OUTPUT | MUX_MODE2)						/* vout1_d1.uart5_txd */
    			VOUT1_D3 (PIN_OUTPUT | MUX_MODE14)					/* vout1_d3.gpio8_3 */
    			VOUT1_D4 (PIN_OUTPUT | MUX_MODE14)					/* vout1_d4.gpio8_4 */
    												
    		>;
    	};
    	
    	uart7_pins: pinmux_uart7_pins {
    		pinctrl-single,pins = <
    			VOUT1_D16 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* vout1_d16.uart7_rxd */
    			//VOUT1_D16 (PIN_OUTPUT | MUX_MODE14)							/* vout1_d16.gpio8_16 */
    			VOUT1_D17 (PIN_OUTPUT | MUX_MODE2)						/* vout1_d17.uart7_txd */		
    			//VOUT1_D17 (PIN_OUTPUT | MUX_MODE14)							/* vout1_d17.gpio8_17 */	
    		>;
    	};
    
    	davinci_mdio_pins_default: pinmux_davinci_mdio_pins_default {
    		pinctrl-single,pins = <
    			/* MDIO */
    				0x190	(	PIN_OUTPUT_PULLUP | MUX_MODE3 )				/* vin2a_d10.mdio_clk */
    				0x194 ( PIN_INPUT_PULLUP | MUX_MODE3 )				/* vin2a_d11.mkio_d */
    		>;
    	};
    
    
    	hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
    		pinctrl-single,pins = <
    			/* this pin is used as a GPIO via mcasp */
    			0x2fc	(PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
    		>;
    	};
    
    	hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
    		pinctrl-single,pins = <
    			0x408	(PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
    			0x40c	(PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
    		>;
    	};
    
    	hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
    		pinctrl-single,pins = <
    			0x408	(PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
    			0x40c	(PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
    		>;
    	};
    
    	dcan1_pins_default: dcan1_pins_default {
    		pinctrl-single,pins = <
    			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* dcan1_tx */
    			0x418   (PULL_UP | MUX_MODE1)		/* wakeup0.dcan1_rx */
    		>;
    	};
    
    	dcan1_pins_sleep: dcan1_pins_sleep {
    		pinctrl-single,pins = <
    			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
    			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
    		>;
    	};
    
    	mmc1_pins_default: pinmux_mmc1_default_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
    			//0x36c (PIN_INPUT | MUX_MODE14)		/* mmc1sdcd.gpio187 */
    		>;
    	};
    
    	mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_hs: pinmux_mmc1_hs_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc2_pins_default: mmc2_pins_default {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc2_pins_hs: pinmux_mmc2_hs_pins {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    };
    
    &dra7_iodelay_core {
    	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
    		pinctrl-single,pins = <
    			0x618 (A_DELAY(572) | G_DELAY(540))	/* CFG_MMC1_CLK_IN */
    			0x624 (A_DELAY(0) | G_DELAY(600))	/* CFG_MMC1_CMD_IN */
    			0x630 (A_DELAY(403) | G_DELAY(120))	/* CFG_MMC1_DAT0_IN */
    			0x63c (A_DELAY(23) | G_DELAY(60))	/* CFG_MMC1_DAT1_IN */
    			0x648 (A_DELAY(25) | G_DELAY(60))	/* CFG_MMC1_DAT2_IN */
    			0x654 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_IN */
    			0x620 (A_DELAY(1525) | G_DELAY(0))	/* CFG_MMC1_CLK_IN */
    			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
    			0x62c (A_DELAY(55) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
    			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
    			0x638 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OUT */
    			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
    			0x644 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OUT */
    			0x64c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
    			0x650 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OUT */
    			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
    			0x65c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OUT */
    		>;
    	};
    
    	mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
    		pinctrl-single,pins = <
    			0x18c (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A19_IN */
    			0x1a4 (A_DELAY(265) | G_DELAY(360))	/* CFG_GPMC_A20_IN */
    			0x1b0 (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A21_IN */
    			0x1bc (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A22_IN */
    			0x1c8 (A_DELAY(287) | G_DELAY(420))	/* CFG_GPMC_A23_IN */
    			0x1d4 (A_DELAY(144) | G_DELAY(240))	/* CFG_GPMC_A24_IN */
    			0x1e0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_IN */
    			0x1ec (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A26_IN */
    			0x1f8 (A_DELAY(120) | G_DELAY(180))	/* CFG_GPMC_A27_IN */
    			0x360 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_IN */
    			0x190 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_OEN */
    			0x194 (A_DELAY(174) | G_DELAY(0))	/* CFG_GPMC_A19_OUT */
    			0x1a8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A20_OEN */
    			0x1ac (A_DELAY(168) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
    			0x1b4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A21_OEN */
    			0x1b8 (A_DELAY(136) | G_DELAY(0))	/* CFG_GPMC_A21_OUT */
    			0x1c0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OEN */
    			0x1c4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OUT */
    			0x1d0 (A_DELAY(879) | G_DELAY(0))	/* CFG_GPMC_A23_OUT */
    			0x1d8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OEN */
    			0x1dc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OUT */
    			0x1e4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OEN */
    			0x1e8 (A_DELAY(34) | G_DELAY(0))	/* CFG_GPMC_A25_OUT */
    			0x1f0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A26_OEN */
    			0x1f4 (A_DELAY(120) | G_DELAY(0))	/* CFG_GPMC_A26_OUT */
    			0x1fc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OEN */
    			0x200 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OUT */
    			0x364 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OEN */
    			0x368 (A_DELAY(11) | G_DELAY(0))	/* CFG_GPMC_CS1_OUT */
    		>;
    	};
    	
    	
    	i2c1_pins_default: pinmux_i2c1_pins {
    		pinctrl-single,pins = <
    			I2C1_SDA (PIN_OUTPUT_PULLUP | MUX_MODE0)  /* i2c1_sda.i2c1_sda */
    			I2C1_SCL (PIN_OUTPUT_PULLUP | MUX_MODE0)  /* i2c1_scl.i2c1_scl */
    		
    		>;
    	};	
    
    	i2c4_pins_default: pinmux_i2c4_pins {
    		pinctrl-single,pins = <
    			MMC1_SDCD (PIN_OUTPUT_PULLUP | MUX_MODE4)  /* mmc1_sdcd.i2c4_sda -> 4 */
    			MMC1_SDWP (PIN_OUTPUT_PULLUP | MUX_MODE4)  /* mmc1_sdwp.i2c4_scl -> 4 */
    
    		>;
    	};
    		
    	mcasp1_pins: mcasp1_pins {
    		pinctrl-single,pins = <
    			MCASP1_ACLKR 	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_0
          MCASP1_FSR    (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_1
    	    MCASP1_AXR3   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_5
    	    MCASP1_AXR4   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_6 
    	    MCASP1_AXR5   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_7 
    	    MCASP1_AXR6   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_8
    	    MCASP1_AXR7   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_9
    		>;
    	};		
    
    	mcasp2_pins: mcasp2_pins {
    		pinctrl-single,pins = <
    			MCASP2_ACLKX  (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated
    			MCASP2_FSX    (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated  
    			MCASP2_AXR0   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated    
    			MCASP2_AXR1   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated    
    			MCASP2_AXR2   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DT_FM3_IBOC_IQ_DI */ 	//gpio6_8			
    			MCASP2_AXR3   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DT_FM3_IBOC_IQ_DQ */ 	//gpio6_9	 
    			MCASP2_AXR5   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DSP_FM_I2C_OUT */ 		//gpio6_7					
    		>;
    	};		
    
    		
    	mcasp3_pins: mcasp3_pins {
    		/* slave */
    		pinctrl-single,pins = <
    			/* audio mcasp3 with loopback test */
    			MCASP3_ACLKX	(PIN_INPUT | MUX_MODE1)			/* mcasp3_aclkr */			// gpio5_13			B18, 0x324
    			MCASP3_FSX	(PIN_INPUT | MUX_MODE1)			/* mcasp3_fsr */			// gpio5_14			F15, 0x328
    			MCASP3_AXR0	(PIN_INPUT           | MUX_MODE0)	/* mcasp3_axr0, mode 0 */		// decidated			B19, 0x32C
    			MCASP3_AXR1	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr1, mode 0 */		// decidated			C17, 0x330
    		>;
    	};		
    	
    	mcasp4_pins: mcasp4_pins {
    		pinctrl-single,pins = <
    			MCASP4_ACLKX 	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// decidated
    			MCASP4_FSX  	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */ 	// decidated  
          MCASP4_AXR0   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// decidated 
    		>;
    	};			
    
    		
    };
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	tps659038: tps659038@58 {
    		compatible = "ti,tps659038";
    		reg = <0x58>;
    
    		tps659038_pmic {
    			compatible = "ti,tps659038-pmic";
    
    			regulators {
    			 /*
    				smps123_reg: smps123 {
    					// VDD_MPU
    					regulator-name = "smps123";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    			  */
    
    				smps12_reg: smps12 {
    					/* VDD_MPU */
    					regulator-name = "smps12";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    				
    				smps3_reg: smps3 {
    					/* VDD_DDR */
    					regulator-name = "smps3";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps45_reg: smps45 {
    					/* VDD_DSPEVE */
    					regulator-name = "smps45";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1150000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps6_reg: smps6 {
    					/* VDD_GPU - over VDD_SMPS6 */
    					regulator-name = "smps6";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps7_reg: smps7 {
    					/* CORE_VDD */
    					regulator-name = "smps7";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1060000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps8_reg: smps8 {
    					/* VDD_IVAHD */
    					regulator-name = "smps8";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps9_reg: smps9 {
    					/* VDDS1V8 */
    					regulator-name = "smps9";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo1_reg: ldo1 {
    					/* LDO1_OUT --> SDIO  */
    					regulator-name = "ldo1";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo2_reg: ldo2 {
    					/* VDD_RTCIO */
    					/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
    					regulator-name = "ldo2";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo3_reg: ldo3 {
    					/* VDDA_1V8_PHY */
    					regulator-name = "ldo3";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo9_reg: ldo9 {
    					/* VDD_RTC */
    					regulator-name = "ldo9";
    					regulator-min-microvolt = <1050000>;
    					regulator-max-microvolt = <1050000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldoln_reg: ldoln {
    					/* VDDA_1V8_PLL */
    					regulator-name = "ldoln";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldousb_reg: ldousb {
    					/* VDDA_3V_USB: VDDA_USBHS33 */
    					regulator-name = "ldousb";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				/* REGEN1 is unused */
    				regen1: regen1 {
    					/* Needed for PMIC internal resources */
    					regulator-name = "regen1";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    
    				regen2: regen2 {
    					/* Needed for PMIC internal resources */
    					regulator-name = "regen2";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				/* REGEN3 is unused */
    
    				sysen1: sysen1 {
    					/* PMIC_REGEN_3V3 */
    					regulator-name = "sysen1";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				sysen2: sysen2 {
    					/* PMIC_REGEN_DDR */
    					regulator-name = "sysen2";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    			};
    		};
    	};
    
    	pcf_lcd: gpio@20 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x20>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	pcf_gpio_21: gpio@21 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x21>;
    		lines-initial-states = <0x1408>;
    		gpio-controller;
    		#gpio-cells = <2>;
    		interrupt-parent = <&gpio6>;
    		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
    		interrupt-controller;
    		#interrupt-cells = <2>;
    	};
    
    
    	tlv320aic3106: tlv320aic3106@18 {
    		status = "disabled";
    		compatible = "ti,tlv320aic3106";
    		reg = <0x18>;
    		adc-settle-ms = <40>;
    		ai3x-micbias-vg = <1>;		/* 2.0V */
    		//status = "okay";
    
    		/* Regulators */
    		AVDD-supply = <&evm_3v3_sw>;
    		IOVDD-supply = <&evm_3v3_sw>;
    		DRVDD-supply = <&evm_3v3_sw>;
    		DVDD-supply = <&aic_dvdd>;
    	};
    };
    
    i2c_p3_exp: &i2c2 {
    	status = "disabled";
    	clock-frequency = <400000>;
    
    	pcf_hdmi: gpio@26 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x26>;
    		lines-initial-states = <0xffeb>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	ov10633@37 {
    		compatible = "ovti,ov10633";
    		reg = <0x37>;
    		status = "disabled";
    		mux-gpios = <&pcf_hdmi 3	GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
    		port {
    			onboardLI: endpoint {
    				remote-endpoint = <&vin1a>;
    				hsync-active = <1>;
    				vsync-active = <1>;
    				pclk-sample = <0>;
    			};
    		};
    	};
    };
    
    &i2c2 {
    	status = "okay";
    	clock-frequency = <400000>;
    };
    
    &i2c3 {
    	status = "disabled";
    	clock-frequency = <3400000>;
    };
    
    &i2c4 {
    	status = "disabled";
    	clock-frequency = <400000>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&i2c4_pins_default>;	
    };
    
    
    &i2c5 {
    	status = "okay";
    	clock-frequency = <400000>;
    };
    
    &mcspi1 {
    	//status = "okay";
    	status = "disabled";
    };
    
    &mcspi2 {
    	//status = "okay";
    	status = "disabled";
    };
    
    &uart1 {
    	status = "okay";
    	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
    			       &dra7_pmx_core 0x3e0>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart1_pins>;
    };
    
    &uart2 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart2_pins>;		
    };
    
    /*
    * &uart3 {
    *	status = "okay";
    *	gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
    * };
    */
    
    &uart3 {
    	status = "okay";
    	//gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart3_pins>;
    };
    
    &uart5 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart5_pins>;
    };
    
    &uart7 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart7_pins>;
    };
    
    
    &mmc1 {
    	status = "okay";
    	pbias-supply = <&pbias_mmc_reg>;
    	vmmc-supply = <&evm_3v3_sd>;
    	vmmc_aux-supply = <&ldo1_reg>;
    	bus-width = <4>;
    	/*
    	 * SDCD signal is not being used here - using the fact that GPIO mode
    	 * is always hardwired.
    	 */
    	/* cd-gpios = <&gpio6 27 0>; */
    	ti,non-removable;
    	pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
    	pinctrl-0 = <&mmc1_pins_default>;
    	pinctrl-1 = <&mmc1_pins_hs>;
    	pinctrl-2 = <&mmc1_pins_sdr12>;
    	pinctrl-3 = <&mmc1_pins_sdr25>;
    	pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
    	sd-uhs-ddr50;
    	sd-uhs-sdr25;
    	sd-uhs-sdr12;
    };
    
    
    &mmc2 {
    	status = "disabled";
    	//status = "okay";
    	vmmc-supply = <&evm_3v3_sw>;
    	bus-width = <8>;
    	pinctrl-names = "default", "hs", "ddr_3_3v";
    	pinctrl-0 = <&mmc2_pins_default>;
    	pinctrl-1 = <&mmc2_pins_hs>;
    	pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
    	mmc-ddr-1_8v;
    };
    
    &mmc4 {
    	//status = "okay";
    	status = "disabled";
    	vmmc-supply = <&vmmcwl_fixed>;
    	bus-width = <4>;
    	cap-power-off-card;
    	keep-power-in-suspend;
    	ti,non-removable;
    
    	#address-cells = <1>;
    	#size-cells = <0>;
    	wlcore: wlcore@0 {
    		compatible = "ti,wlcore";
    		reg = <2>;
    		interrupt-parent = <&gpio5>;
    		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    	};
    };
    
    &cpu0 {
    	cpu0-voltdm = <&voltdm_mpu>;
    	voltage-tolerance = <1>;
    };
    
    &voltdm_mpu {
    	// OTP 82
    	//vdd-supply = <&smps123_reg>;
    	
    	// OTP60
    	vdd-supply = <&smps12_reg>;	
    };
    
    &voltdm_dspeve {
    	vdd-supply = <&smps45_reg>;
    };
    
    &voltdm_gpu {
    	vdd-supply = <&smps6_reg>;
    };
    
    &voltdm_ivahd {
    	vdd-supply = <&smps8_reg>;
    };
    
    &voltdm_core {
    	vdd-supply = <&smps7_reg>;
    };
    
    &qspi {
    	status = "okay";
    
    	spi-max-frequency = <48000000>;
    	m25p80@0 {
    		status = "disabled";
    		compatible = "s25fl256s1";
    		spi-max-frequency = <48000000>;
    		reg = <0>;
    		spi-tx-bus-width = <1>;
    		spi-rx-bus-width = <4>;
    		spi-cpol;
    		spi-cpha;
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		/* MTD partition table.
    		 * The ROM checks the first four physical blocks
    		 * for a valid file to boot and the flash here is
    		 * 64KiB block size.
    		 */
    		partition@0 {
    			label = "QSPI.SPL";
    			reg = <0x00000000 0x000010000>;
    		};
    		partition@1 {
    			label = "QSPI.SPL.backup1";
    			reg = <0x00010000 0x00010000>;
    		};
    		partition@2 {
    			label = "QSPI.SPL.backup2";
    			reg = <0x00020000 0x00010000>;
    		};
    		partition@3 {
    			label = "QSPI.SPL.backup3";
    			reg = <0x00030000 0x00010000>;
    		};
    		partition@4 {
    			label = "QSPI.u-boot";
    			reg = <0x00040000 0x00100000>;
    		};
    		partition@5 {
    			label = "QSPI.u-boot-spl-os";
    			reg = <0x00140000 0x00080000>;
    		};
    		partition@6 {
    			label = "QSPI.u-boot-env";
    			reg = <0x001c0000 0x00010000>;
    		};
    		partition@7 {
    			label = "QSPI.u-boot-env.backup1";
    			reg = <0x001d0000 0x0010000>;
    		};
    		partition@8 {
    			label = "QSPI.kernel";
    			reg = <0x001e0000 0x0800000>;
    		};
    		partition@9 {
    			label = "QSPI.file-system";
    			reg = <0x009e0000 0x01620000>;
    		};
    	};
    };
    
    &omap_dwc3_1 {
    		status = "ok";
    	extcon = <&extcon_usb1>;
    };
    
    &omap_dwc3_2 {
    		status = "ok";
    	extcon = <&extcon_usb2>;
    };
    
    &usb1 {
    dr_mode = "otg" ;
    };
    
    &usb2 {
    dr_mode = "otg" ;
    };
    
    
    &mac {
    	pinctrl-names = "default";
        pinctrl-0 = <&cpsw_default>;
    	status = "okay";
    	dual_emac;
    	ti,no-idle;
    };
    
    &davinci_mdio {
    	pinctrl-names = "default";
    	pinctrl-0 = <&davinci_mdio_pins_default>;
    };
    
    &cpsw_emac0 {
    	phy_id = <&davinci_mdio>, <0>;
    	phy-mode = "rgmii";
    	dual_emac_res_vlan = <1>;
    };
    
    &cpsw_emac1 {
    	phy_id = <&davinci_mdio>, <21>;
    	phy-mode = "rgmii";
    	dual_emac_res_vlan = <2>;
    };
    
    
    &elm {
    	status = "okay";
    };
    
    &gpmc {
    	status = "disabled";
    	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
    	nand@0,0 {
    		reg = <0 0 4>;		/* device IO registers */
    		ti,nand-ecc-opt = "bch8";
    		ti,elm-id = <&elm>;
    		nand-bus-width = <16>;
    		gpmc,device-width = <2>;
    		gpmc,sync-clk-ps = <0>;
    		gpmc,cs-on-ns = <0>;
    		gpmc,cs-rd-off-ns = <80>;
    		gpmc,cs-wr-off-ns = <80>;
    		gpmc,adv-on-ns = <0>;
    		gpmc,adv-rd-off-ns = <60>;
    		gpmc,adv-wr-off-ns = <60>;
    		gpmc,we-on-ns = <10>;
    		gpmc,we-off-ns = <50>;
    		gpmc,oe-on-ns = <4>;
    		gpmc,oe-off-ns = <40>;
    		gpmc,access-ns = <40>;
    		gpmc,wr-access-ns = <80>;
    		gpmc,rd-cycle-ns = <80>;
    		gpmc,wr-cycle-ns = <80>;
    		gpmc,bus-turnaround-ns = <0>;
    		gpmc,cycle2cycle-delay-ns = <0>;
    		gpmc,clk-activation-ns = <0>;
    		gpmc,wait-monitoring-ns = <0>;
    		gpmc,wr-data-mux-bus-ns = <0>;
    		/* MTD partition table */
    		/* All SPL-* partitions are sized to minimal length
    		 * which can be independently programmable. For
    		 * NAND flash this is equal to size of erase-block */
    		#address-cells = <1>;
    		#size-cells = <1>;
    		partition@0 {
    			label = "NAND.SPL";
    			reg = <0x00000000 0x000020000>;
    		};
    		partition@1 {
    			label = "NAND.SPL.backup1";
    			reg = <0x00020000 0x00020000>;
    		};
    		partition@2 {
    			label = "NAND.SPL.backup2";
    			reg = <0x00040000 0x00020000>;
    		};
    		partition@3 {
    			label = "NAND.SPL.backup3";
    			reg = <0x00060000 0x00020000>;
    		};
    		partition@4 {
    			label = "NAND.u-boot-spl-os";
    			reg = <0x00080000 0x00040000>;
    		};
    		partition@5 {
    			label = "NAND.u-boot";
    			reg = <0x000c0000 0x00100000>;
    		};
    		partition@6 {
    			label = "NAND.u-boot-env";
    			reg = <0x001c0000 0x00020000>;
    		};
    		partition@7 {
    			label = "NAND.u-boot-env.backup1";
    			reg = <0x001e0000 0x00020000>;
    		};
    		partition@8 {
    			label = "NAND.kernel";
    			reg = <0x00200000 0x00800000>;
    		};
    		partition@9 {
    			label = "NAND.file-system";
    			reg = <0x00a00000 0x0f600000>;
    		};
    	};
    };
    
    &gpio2 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*	
    	gpio2_0 {
    		gpio-hog;
    		gpios = < 0 0 >;
    		output-high;
    		line-name = "MD_12VPA_EN";
    	};
    
    	gpio2_1 {
    		gpio-hog;
    		gpios = < 1 0 >;
    		output-high;
    		line-name = "MD_12VPB_EN";
    	};
    	
    	gpio2_2 {
    		gpio-hog;
    		gpios = < 2 0 >;
    		output-high;
    		line-name = "SOC_POWER_ON";
    	};
    */	
    };
    
    &gpio3 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*
    	gpio3_6 {
    		gpio-hog;
    		gpios = < 6 0 >;
    		output-high;
    		line-name = "SOC_RESET_IN";
    	};
    	
    	gpio3_29 {
    		gpio-hog;
    		gpios = < 29 0 >;
    		output-high;
    		line-name = "AB_DEBUG_MUX_AB_USB";
    	};
    */	
    };
    
    &gpio7 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*	
    	gpio7_0 {
    		gpio-hog;
    		gpios = < 0 0 >;
    		output-high;
    		line-name = "BOOT_MODE0";	
    	};	
    
    	gpio7_1 {
    		gpio-hog;
    		gpios = < 1 0 >;
    		output-low;
    		line-name = "BOOT_MODE1";
    	};
    */	
    };
    
    &gpio8 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*
    	gpio8_9 {
    		gpio-hog;
    		gpios = < 9 0 >;
    		output-high;
    		line-name = "FPGA_RST_N";
    	};
    */
    };
    
    &dss {
    	//status = "ok";
    	status = "disabled";
    	vdda_video-supply = <&ldoln_reg>;
    };
    
    &hdmi {
    	//status = "ok";
    	status = "disabled";
    	vdda-supply = <&ldo3_reg>;
    
    	port {
    		hdmi_out: endpoint {
    			remote-endpoint = <&tpd12s015_in>;
    		};
    	};
    };
    
    &dcan1 {
    	//status = "ok";
    	status = "disabled";
    	pinctrl-names = "default", "sleep";
    	pinctrl-0 = <&dcan1_pins_default>;
    	pinctrl-1 = <&dcan1_pins_sleep>;
    };
    
    &mailbox5 {
    	status = "okay";
    	mbox_ipu1_legacy: mbox_ipu1_legacy {
    		status = "okay";
    	};
    	mbox_dsp1_legacy: mbox_dsp1_legacy {
    		status = "okay";
    	};
    };
    
    &mailbox6 {
    	status = "okay";
    	mbox_ipu2_legacy: mbox_ipu2_legacy {
    		status = "okay";
    	};
    	mbox_dsp2_legacy: mbox_dsp2_legacy {
    		status = "okay";
    	};
    };
    
    &mmu0_dsp1 {
    	status = "okay";
    };
    
    &mmu1_dsp1 {
    	status = "okay";
    };
    
    &mmu0_dsp2 {
    	status = "okay";
    };
    
    &mmu1_dsp2 {
    	status = "okay";
    };
    
    &mmu_ipu1 {
    	status = "okay";
    };
    
    &mmu_ipu2 {
    	status = "okay";
    };
    
    &ipu2 {
    	status = "okay";
    	memory-region = <&ipu2_cma_pool>;
    	mboxes = <&mailbox6 &mbox_ipu2_legacy>;
    	timers = <&timer3>;
    	watchdog-timers = <&timer4>, <&timer9>;
    };
    
    &ipu1 {
    	status = "okay";
    	memory-region = <&ipu1_cma_pool>;
    	mboxes = <&mailbox5 &mbox_ipu1_legacy>;
    	timers = <&timer11>;
    	watchdog-timers = <&timer7>, <&timer8>;
    };
    
    &dsp1 {
    	status = "okay";
    	memory-region = <&dsp1_cma_pool>;
    	mboxes = <&mailbox5 &mbox_dsp1_legacy>;
    	timers = <&timer5>;
    	watchdog-timers = <&timer10>;
    };
    
    &dsp2 {
    	status = "okay";
    	memory-region = <&dsp2_cma_pool>;
    	mboxes = <&mailbox6 &mbox_dsp2_legacy>;
    	timers = <&timer6>;
    };
    
    &atl {
    	status = "okay";
    
    	atl2 {
    		bws = <DRA7_ATL_WS_MCASP2_FSX>;
    		aws = <DRA7_ATL_WS_MCASP3_FSX>;
    	};
    };
    
    // LOUIS ADD
    &mcasp1 {
    
    	//pinctrl-names = "default";
    	//pinctrl-0 = <&mcasp1_pins>;
    		
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 16 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		0 0 0 1  1 1 2 2
    		0 0 0 0  0 0 0 0
    	>;
    	tx-num-evt = <8>;			// fifo event level
    	rx-num-evt = <8>;
    };
    
    // LOUIS ADD
    &mcasp2 {
    
    	//pinctrl-names = "default";
    	//pinctrl-0 = <&mcasp2_pins>;
    		
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 16 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 2 1  0 1 0 0
    		0 0 0 0  0 0 0 0
    	>;
    	tx-num-evt = <8>;			// fifo event level
    	rx-num-evt = <8>;
    };
    
    &mcasp3 {
    	#sound-dai-cells = <0>;
    	fck_parent = "atl_clkin2_ck";
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcasp3_pins>;
    
    	status = "okay";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    // LOUIS ADD
    &mcasp4 {
    
    	//pinctrl-names = "default";
    	//pinctrl-0 = <&mcasp4_pins>;
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		1 0 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    
    &mcasp7 {
    	#sound-dai-cells = <0>;
    
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;  /* MCASP_IIS_MODE */
    	tdm-slots = <4>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    &mcasp8 {
    	/* not used for audio. only the AXR2 pin is used as GPIO */
    	status = "disabled";
    };
    
    &usb2_phy1 {
    	phy-supply = <&ldousb_reg>;
    };
    
    &usb2_phy2 {
    	phy-supply = <&ldousb_reg>;
    };
    
    &vip1 {
    	status = "okay";
    };
    
    video_in: &vin1a {
    	//status = "okay";
    	status = "disabled";
    	endpoint@0 {
    		slave-mode;
    		remote-endpoint = <&onboardLI>;
    	};
    };
    
    #include "dra7xx-jamr3.dtsi"
    
    //
    //&tvp_5158{
    //	mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>,	/*CAM_FPD_MUX_S0*/
    //			<&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>;	/*SEL_TVP_FPD*/
    //};
    

    Adapt_Board_dra72-evm-common.dtsi.txt
    /*
     * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    /dts-v1/;
    
    #include "dra72x.dtsi"
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clk/ti-dra7-atl.h>
    
    / {
    	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
    
    	aliases {
    		display0 = &hdmi0;
    		display1 = &lcd2;
    		sound0 = &snd0;
    		sound1 = &hdmi;
    	};
    
    	evm_3v3_sw: fixedregulator-evm_3v3 {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	aic_dvdd: fixedregulator-aic_dvdd {
    		/* TPS77018DBVT */
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd";
    		vin-supply = <&evm_3v3_sw>;
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    	};
    
    	evm_3v3_sd: fixedregulator-sd {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sd";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    		enable-active-high;
    	};
    
    #if 0
    	extcon_usb1: extcon_usb1 {
    		compatible = "linux,extcon-usb-gpio";
    		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
    	};
    
    	extcon_usb2: extcon_usb2 {
    		compatible = "linux,extcon-usb-gpio";
    		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
    	};
    #endif
    
    	hdmi0: connector {
    		compatible = "hdmi-connector";
    		status = "disabled";
    		label = "hdmi";
    
    		type = "a";
    
    		port {
    			hdmi_connector_in: endpoint {
    				remote-endpoint = <&tpd12s015_out>;
    			};
    		};
    	};
    
    	tpd12s015: encoder {
    		compatible = "ti,tpd12s015";
    		status = "disabled";
    
    		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
    			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
    			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
    
    		ports {
    			#address-cells = <1>;
    			#size-cells = <0>;
    
    			port@0 {
    				reg = <0>;
    
    				tpd12s015_in: endpoint {
    					remote-endpoint = <&hdmi_out>;
    				};
    			};
    
    			port@1 {
    				reg = <1>;
    
    				tpd12s015_out: endpoint {
    					remote-endpoint = <&hdmi_connector_in>;
    				};
    			};
    		};
    	};
    
    	btsco: btsco@0 {
    		#sound-dai-cells = <0>;
    		compatible = "delta,dfbmcs320";
    		status = "okay";
    	};
    
    	snd0: sound@0 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "DRA7xx-EVM";
    #if 0
    		/* we do not have codec */
    		simple-audio-card,mclk-fs = <256>;
    #endif
    		simple-audio-card,widgets =
    			"Headphone", "Headphone Jack",
    			"Line", "Line Out",
    			"Microphone", "Mic Jack",
    			"Line", "Line In";
    		simple-audio-card,routing =
    			"Headphone Jack",       "HPLOUT",
    			"Headphone Jack",       "HPROUT",
    			"Line Out",		"LLOUT",
    			"Line Out",		"RLOUT",
    			"MIC3L",		"Mic Jack",
    			"MIC3R",		"Mic Jack",
    			"Mic Jack",		"Mic Bias",
    			"LINE1L",               "Line In",
    			"LINE1R",               "Line In";
    		status = "okay";
    
    #if 1
    		simple-audio-card,dai-link@0 {
    			format = "i2s";
    			bitclock-master = <&sound0_master>;
    			frame-master = <&sound0_master>;
    			bitclock-inversion;
    
    			sound0_master: cpu {
    				sound-dai = <&mcasp3>;
    #if 1
    				system-clock-frequency = <8192000>;
    #endif
    			};
    
    			codec {
    				sound-dai = <&btsco>;
    			};
    		};
    #else
    		simple-audio-card,format = "i2s";
    		simple-audio-card,bitclock-master = <&sound0_master>;
    		simple-audio-card,frame-master = <&sound0_master>;
    		simple-audio-card,bitclock-inversion;
    
    		sound0_master: simple-audio-card,cpu {
    			sound-dai = <&mcasp3>;
    			system-clock-frequency = <11289600>;
    		};
    
    		simple-audio-card,codec {
    			sound-dai = <&btsco>;
    			clocks = <&atl_clkin2_ck>;
    		};
    #endif
    	};
    
    #if 0
    	// GPIO5_8 is used for TDM pin
    	vmmcwl_fixed: fixedregulator-mmcwl {
    		compatible = "regulator-fixed";
    		regulator-name = "vmmcwl_fixed";
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    		gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
    		enable-active-high;
    	};
    #endif
    };
    
    &dra7_pmx_core {
    	mcasp3_pins: mcasp3_pins {
    		/* mcasp3 loopback test (Adapt Board needs to rework) */
    		pinctrl-single,pins = <
    			0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* dedicate: B19_MCASP3_AXR0 */
    			0x330 (PIN_INPUT           | MUX_MODE0)	/* dedicate: C17_MCASP3_AXR1 */
    			/* clk master */
    			0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* B18_MCASP3_ACLKX*/
    			0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* F15_MCASP3_FSX */
    		>;
    	};
    
            tps65917_pins_default: tps65917_pins_default {
                    pinctrl-single,pins = <
                            0x424 (PIN_INPUT_PULLUP | MUX_MODE1)    /* wakeup3.sys_nirq1 */
                    >;   
            };
    
    	mmc1_pins_default: mmc1_pins_default {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc2_pins_default: mmc2_pins_default {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc4_pins_default: mmc4_pins_default {
    		pinctrl-single,pins = <
    			0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
    			0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
    			0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
    			0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
    			0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
    			0x3fC (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
    		>;
    	};
    
    	dcan1_pins_default: dcan1_pins_default {
    		pinctrl-single,pins = <
    			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
    			0x418   (PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
    		>;
    	};
    
    	dcan1_pins_sleep: dcan1_pins_sleep {
    		pinctrl-single,pins = <
    			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
    			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
    		>;
    	};
    
    #if 0
    	// GPIO5_8 function in TDM
    	wlan_pins: pinmux_wlan_pins {
    		pinctrl-single,pins = <
    			0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_ctsn.mmc4_clk */
    			0x3ec (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_rtsn.mmc4_cmd */
    			0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_rxd.mmc4_dat0 */
    			0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_txd.mmc4_dat1 */
    			0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_ctsn.mmc4_dat2 */
    			0x3fc (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_rtsn.mmc4_dat3 */
    			0x2cc (PIN_OUTPUT | MUX_MODE14)		/* mcasp1_axr6.gpio5_8 - WLAN_EN */
    		>;
    	};
    #endif
    
    	wlirq_pins: pinmux_wlirq_pins {
    		pinctrl-single,pins = <
    			0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
    		>;
    	};
    };
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	tps65917: tps65917@58 {
    		compatible = "ti,tps65917";
    		reg = <0x58>;
    
    #if 0
    		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
    #else
                    pinctrl-names = "default";
                    pinctrl-0 = <&tps65917_pins_default>;
                    interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
                                            &dra7_pmx_core 0x424>;
                    interrupt-parent = <&gic>;
    #endif
    		interrupt-controller;
    		#interrupt-cells = <2>;
    
    		ti,system-power-controller;
    
    		tps65917_pmic {
    			compatible = "ti,tps65917-pmic";
    
    			tps65917_regulators: regulators {
    				smps1_reg: smps1 {
    					/* VDD_MPU */
    					regulator-name = "smps1";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps2_reg: smps2 {
    					/* VDD_CORE */
    					regulator-name = "smps2";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1150000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps3_reg: smps3 {
    					/* VDD_GPU IVA DSPEVE */
    					regulator-name = "smps3";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps4_reg: smps4 {
    					/* VDDS1V8 */
    					regulator-name = "smps4";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps5_reg: smps5 {
    					/* VDD_DDR */
    					regulator-name = "smps5";
    					regulator-min-microvolt = <1350000>;
    					regulator-max-microvolt = <1350000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo1_reg: ldo1 {
    					/* LDO1_OUT --> SDIO  */
    					regulator-name = "ldo1";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-always-on;
    					regulator-boot-on;
    					regulator-allow-bypass;
    				};
    
    				ldo3_reg: ldo3 {
    					/* VDDA_1V8_PHY */
    					regulator-name = "ldo3";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo5_reg: ldo5 {
    					/* VDDA_1V8_PLL */
    					regulator-name = "ldo5";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo4_reg: ldo4 {
    					/* VDDA_3V_USB: VDDA_USBHS33 */
    					regulator-name = "ldo4";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    				};
    			};
    		};
    
    		tps65917_power_button {
    			compatible = "ti,palmas-pwrbutton";
    			interrupt-parent = <&tps65917>;
    			interrupts = <1 IRQ_TYPE_NONE>;
    			wakeup-source;
    			ti,palmas-long-press-seconds = <6>;
    		};
    	};
    
    	pcf_lcd: gpio@20 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x20>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	pcf_gpio_21: gpio@21 {
    		status = "disabled";
    		compatible = "ti,pcf8575";
    		reg = <0x21>;
    		lines-initial-states = <0x1408>;
    		gpio-controller;
    		#gpio-cells = <2>;
    
    		interrupt-controller;
    		#interrupt-cells = <2>;
    	};
    
    	tlv320aic3106: tlv320aic3106@19 {
    		#sound-dai-cells = <0>;
    		compatible = "ti,tlv320aic3106";
    		reg = <0x19>;
    		adc-settle-ms = <40>;
    		ai3x-micbias-vg = <1>;		/* 2.0V */
    		status = "okay";
    
    		/* Regulators */
    		AVDD-supply = <&evm_3v3_sw>;
    		IOVDD-supply = <&evm_3v3_sw>;
    		DRVDD-supply = <&evm_3v3_sw>;
    		DVDD-supply = <&aic_dvdd>;
    	};
    };
    
    i2c_p3_exp: &i2c5 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	pcf_hdmi: pcf8575@26 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x26>;
    		gpio-controller;
    		#gpio-cells = <2>;
    		/*
    		 * initial state is used here to keep the mdio interface
    		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
    		 * VIN2_S0 driven high otherwise Ethernet stops working
    		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
    		 */
    		lines-initial-states = <0x0f2b>;
    
    		p1 {
    			/* vin6_sel_s0: high: VIN6, low: audio */
    			gpio-hog;
    			gpios = <1 GPIO_ACTIVE_HIGH>;
    			output-low;
    			line-name = "vin6_sel_s0";
    		};
    	};
    };
    
    &mcspi1 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {    
        spi-max-frequency = <16000000>;
        reg = <0>; 
            compatible = "rohm,dh2228fv";   
            status = "okay" ; 
            };   
            spidev@1
            {    
        spi-max-frequency = <16000000>;
        reg = <1>; 
            compatible = "rohm,dh2228fv";
            status = "okay" ; 
            };     
            spidev@3
            {    
        spi-max-frequency = <16000000>;
        reg = <3>; 
            compatible = "rohm,dh2228fv";   
            status = "okay" ; 
            };
    };
    
    &mcspi2 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {
        spi-max-frequency = <16000000>;
        reg = <0>;
            compatible = "rohm,dh2228fv";
            };
    };
    
    &mcspi3 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {
        spi-max-frequency = <16000000>;
        reg = <0>;
            compatible = "rohm,dh2228fv";
            };
    };
    
    &uart1 {
    	status = "okay";
    	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
    			      <&dra7_pmx_core 0x3e0>;
    };
    
    &uart3 {
    	status = "okay";
    };
    
    &elm {
    	status = "okay";
    };
    
    &gpmc {
    	/*
    	 * For the existing IOdelay configuration via U-Boot we don't
    	 * support NAND on dra72-evm. Keep it disabled. Enabling it
    	 * requires a different configuration by U-Boot.
    	 */
    	status = "disabled";
    	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
    	nand@0,0 {
    		/* To use NAND, DIP switch SW5 must be set like so:
    		 * SW5.1 (NAND_SELn) = ON (LOW)
    		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
    		 */
    		compatible = "ti,omap2-nand";
    		reg = <0 0 4>;          /* device IO registers */
    		interrupt-parent = <&gpmc>;
    		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
    			     <1 IRQ_TYPE_NONE>; /* termcount */
    		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */	/* device IO registers */
    		ti,nand-ecc-opt = "bch8";
    		ti,elm-id = <&elm>;
    		nand-bus-width = <16>;
    		gpmc,device-width = <2>;
    		gpmc,sync-clk-ps = <0>;
    		gpmc,cs-on-ns = <0>;
    		gpmc,cs-rd-off-ns = <80>;
    		gpmc,cs-wr-off-ns = <80>;
    		gpmc,adv-on-ns = <0>;
    		gpmc,adv-rd-off-ns = <60>;
    		gpmc,adv-wr-off-ns = <60>;
    		gpmc,we-on-ns = <10>;
    		gpmc,we-off-ns = <50>;
    		gpmc,oe-on-ns = <4>;
    		gpmc,oe-off-ns = <40>;
    		gpmc,access-ns = <40>;
    		gpmc,wr-access-ns = <80>;
    		gpmc,rd-cycle-ns = <80>;
    		gpmc,wr-cycle-ns = <80>;
    		gpmc,bus-turnaround-ns = <0>;
    		gpmc,cycle2cycle-delay-ns = <0>;
    		gpmc,clk-activation-ns = <0>;
    		gpmc,wait-monitoring-ns = <0>;
    		gpmc,wr-data-mux-bus-ns = <0>;
    		/* MTD partition table */
    		/* All SPL-* partitions are sized to minimal length
    		 * which can be independently programmable. For
    		 * NAND flash this is equal to size of erase-block */
    		#address-cells = <1>;
    		#size-cells = <1>;
    		partition@0 {
    			label = "NAND.SPL";
    			reg = <0x00000000 0x000020000>;
    		};
    		partition@1 {
    			label = "NAND.SPL.backup1";
    			reg = <0x00020000 0x00020000>;
    		};
    		partition@2 {
    			label = "NAND.SPL.backup2";
    			reg = <0x00040000 0x00020000>;
    		};
    		partition@3 {
    			label = "NAND.SPL.backup3";
    			reg = <0x00060000 0x00020000>;
    		};
    		partition@4 {
    			label = "NAND.u-boot-spl-os";
    			reg = <0x00080000 0x00040000>;
    		};
    		partition@5 {
    			label = "NAND.u-boot";
    			reg = <0x000c0000 0x00100000>;
    		};
    		partition@6 {
    			label = "NAND.u-boot-env";
    			reg = <0x001c0000 0x00020000>;
    		};
    		partition@7 {
    			label = "NAND.u-boot-env.backup1";
    			reg = <0x001e0000 0x00020000>;
    		};
    		partition@8 {
    			label = "NAND.kernel";
    			reg = <0x00200000 0x00800000>;
    		};
    		partition@9 {
    			label = "NAND.file-system";
    			reg = <0x00a00000 0x0f600000>;
    		};
    	};
    };
    
    &usb2_phy1 {
    	phy-supply = <&ldo4_reg>;
    };
    
    &usb2_phy2 {
    	phy-supply = <&ldo4_reg>;
    };
    
    &omap_dwc3_1 {
    //	extcon = <&extcon_usb1>;
    };
    
    &omap_dwc3_2 {
    //	extcon = <&extcon_usb2>;
    };
    
    &usb1 {
    	status = "ok";
    	dr_mode = "host";
    };
    
    &usb2 {
    	status = "ok";
    	dr_mode = "host";
    };
    
    &usb3 {
    	status = "disabled";
    };
    
    &mmc1 {
    	status = "okay";
    
    	vmmc-supply = <&evm_3v3_sw>;
    	vmmc_aux-supply = <&ldo1_reg>;
    	bus-width = <4>;
    	/*
    	 * SDCD signal is not being used here - using the fact that GPIO mode
    	 * is a viable alternative
    	 */
    	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
    	max-frequency = <192000000>;
    };
    
    &mmc2 {
    	/* SW5-3 in ON position */
    	status = "okay";
    
    	vmmc-supply = <&evm_3v3_sw>;
    	bus-width = <8>;
    	ti,non-removable;
    	max-frequency = <192000000>;
    };
    
    &mmc4 {
    #if 1
            status = "okay";
    
            bus-width = <4>; 
            pinctrl-names = "default";
            pinctrl-0 = <&mmc4_pins_default>;
    	vmmc-supply = <&evm_3v3_sw>;
    #else
    	status = "okay";
    	vmmc-supply = <&vmmcwl_fixed>;
    	bus-width = <4>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&wlan_pins &wlirq_pins>;
    	cap-power-off-card;
    	keep-power-in-suspend;
    	ti,non-removable;
    
    	#address-cells = <1>;
    	#size-cells = <0>;
    	wlcore: wlcore@0 {
    		compatible = "ti,wl1835";
    		reg = <2>;
    		interrupt-parent = <&gpio5>;
    		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    	};
    #endif
    };
    
    &mac {
    	status = "okay";
    };
    
    &dcan1 {
    	status = "ok";
    };
    
    &qspi {
    	status = "okay";
    
    	spi-max-frequency = <64000000>;
    	m25p80@0 {
    		compatible = "s25fl256s1";
    		spi-max-frequency = <64000000>;
    		reg = <0>;
    		spi-tx-bus-width = <1>;
    		spi-rx-bus-width = <4>;
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		/* MTD partition table.
    		 * The ROM checks the first four physical blocks
    		 * for a valid file to boot and the flash here is
    		 * 64KiB block size.
    		 */
    		partition@0 {
    			label = "QSPI.SPL";
    			reg = <0x00000000 0x000040000>;
    		};
    		partition@1 {
    			label = "QSPI.u-boot";
    			reg = <0x00040000 0x00100000>;
    		};
    		partition@2 {
    			label = "QSPI.u-boot-spl-os";
    			reg = <0x00140000 0x00080000>;
    		};
    		partition@3 {
    			label = "QSPI.u-boot-env";
    			reg = <0x001c0000 0x00010000>;
    		};
    		partition@4 {
    			label = "QSPI.u-boot-env.backup1";
    			reg = <0x001d0000 0x0010000>;
    		};
    		partition@5 {
    			label = "QSPI.kernel";
    			reg = <0x001e0000 0x0800000>;
    		};
    		partition@6 {
    			label = "QSPI.file-system";
    			reg = <0x009e0000 0x01620000>;
    		};
    	};
    };
    
    &hdmi {
    	status = "disabled";
    
    	port {
    		hdmi_out: endpoint {
    			remote-endpoint = <&tpd12s015_in>;
    		};
    	};
    };
    
    &atl {
    	assigned-clocks = <&abe_dpll_sys_clk_mux>,
    			  <&atl_gfclk_mux>,
    			  <&dpll_abe_ck>,
    			  <&dpll_abe_m2x2_ck>,
    			  <&atl_clkin1_ck>,
    			  <&atl_clkin2_ck>;
    	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
    #if 0
    	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
    			       <11289600>, <11289600>;
    #else
    	assigned-clock-rates = <0>, <0>, <122880000>, <245760000>,
    			       <8192000>, <8192000>;
    #endif
    
    #if 0
    	status = "okay";
    #else
    	status = "disabled";
    #endif
    
    	atl2 {
    		bws = <DRA7_ATL_WS_MCASP2_FSX>;
    		aws = <DRA7_ATL_WS_MCASP3_FSX>;
    	};
    };
    
    &mcasp3 {
    	#sound-dai-cells = <0>;
    	fck_parent = "atl_clkin2_ck";
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcasp3_pins>;
    
    	status = "okay";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		1 2 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    &mailbox5 {
    	status = "okay";
    	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
    		status = "okay";
    	};
    	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
    		status = "okay";
    	};
    };
    
    &mailbox6 {
    	status = "okay";
    	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
    		status = "okay";
    	};
    };
    
    &mmu0_dsp1 {
    	status = "okay";
    };
    
    &mmu1_dsp1 {
    	status = "okay";
    };
    
    &mmu_ipu1 {
    	status = "okay";
    };
    
    &mmu_ipu2 {
    	status = "okay";
    };
    
    &ipu2 {
    	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
    	timers = <&timer3>;
    	watchdog-timers = <&timer4>, <&timer9>;
    };
    
    &ipu1 {
    	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
    	timers = <&timer11>;
    	watchdog-timers = <&timer7>, <&timer8>;
    };
    
    &dsp1 {
    	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
    	timers = <&timer5>;
    	watchdog-timers = <&timer10>;
    };
    
    &oppdm_mpu {
    	vdd-supply = <&smps1_reg>;
    };
    
    &oppdm_core {
    	vdd-supply = <&smps2_reg>;
    };
    
    &oppdm_dspeve {
    	vdd-supply = <&smps3_reg>;
    };
    
    &oppdm_gpu {
    	vdd-supply = <&smps3_reg>;
    };
    
    &oppdm_ivahd {
    	vdd-supply = <&smps3_reg>;
    };
    

    Could you please help this issue.

    Thank you.

    BRs

    Louis

  • The device-tree settings of the carrier board's simple card is wrong. McASP3 is set to be master, when the codec is the one that should be master.

    simple-audio-card,dai-link@0 {
        format = "i2s";
        bitclock-master = <&sound0_master>;     <- McASP3 is not the master
        frame-master = <&sound0_master>;        <- McASP3 is not the master
        bitclock-inversion;
    
        sound0_master: cpu {
            sound-dai = <&mcasp3>;
            system-clock-frequency = <8192000>;
        };
    
        codec {
            sound-dai = <&btsco>;
        };

    The device-tree settings of the adapt board look ok. McASP3 is properly set as the master of the audio link.

    There are two sets of McASP3 pinmux settings in the carrier board file:

    MCASP3_ACLKX (PIN_INPUT | MUX_MODE1) /* mcasp3_aclkr, */ // B18, 0x324
    MCASP3_FSX   (PIN_INPUT | MUX_MODE1) /* mcasp3_fsr, */ // F15, 0x328
    
    
    MCASP3_AXR0 (PIN_INPUT           | MUX_MODE0)	/* mcasp3_axr0, mode 0 */
    MCASP3_AXR1 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr1, mode 0 */
    

    The first set is incorrect, the second one is correct. The Linux driver configures McASP is synchronous mode, so the BCLK and FSYNC signals are fed via ACLKX/FSX even for the RX path. So the muxmode must be 0 (aclkx, fsx).

    Also, the fck_parent property is different between kernels 3.14 and 4.4. In kernel-3.14, fck_parent is a string with the clock name, in kernel-4.4 is a phandle of the clock node. This property is more important for the McASP instance that is master, although it must be fixed in both cases (master and slave).

  • Hi Misael,

    1. After changing DTS settings, both MCASP3 interfaces in CB and AB can do connection test. Thank you very much.

    2. Now I need to activate MCASP4 interfaces in CB and AB. I reference kernel document and add second dai link in "simple-audio-card" node and mcasp4 control pins both in CB, AB. They still have different error symptons.CB has kernel panic issue and AB has error MCASP4_AXR0 issue (MCASP4_ACLKX and MCASP4_FSX are correct)

    3. The test topology:

    @ MCASP4 in CB to be slave, and to be Master in AB

    @ MCASP4 only use AXR0 and CB capture and AB playback.

    4. Informations:

    4.1 AB DTS file

    6787.dra72-evm-common.dtsi.txt
    /*
     * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    /dts-v1/;
    
    #include "dra72x.dtsi"
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clk/ti-dra7-atl.h>
    
    / {
    	compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
    
    	aliases {
    		display0 = &hdmi0;
    		display1 = &lcd2;
    		sound0 = &snd0;
    		sound1 = &hdmi;
    	};
    
    	evm_3v3_sw: fixedregulator-evm_3v3 {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	aic_dvdd: fixedregulator-aic_dvdd {
    		/* TPS77018DBVT */
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd";
    		vin-supply = <&evm_3v3_sw>;
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    	};
    
    	evm_3v3_sd: fixedregulator-sd {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sd";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    		enable-active-high;
    	};
    
    #if 0
    	extcon_usb1: extcon_usb1 {
    		compatible = "linux,extcon-usb-gpio";
    		id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
    	};
    
    	extcon_usb2: extcon_usb2 {
    		compatible = "linux,extcon-usb-gpio";
    		id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
    	};
    #endif
    
    	hdmi0: connector {
    		compatible = "hdmi-connector";
    		status = "disabled";
    		label = "hdmi";
    
    		type = "a";
    
    		port {
    			hdmi_connector_in: endpoint {
    				remote-endpoint = <&tpd12s015_out>;
    			};
    		};
    	};
    
    	tpd12s015: encoder {
    		compatible = "ti,tpd12s015";
    		status = "disabled";
    
    		gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>,	/* P4, CT CP HPD */
    			<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>,	/* P5, LS OE */
    			<&gpio7 12 GPIO_ACTIVE_HIGH>;	/* gpio7_12/sp1_cs2, HPD */
    
    		ports {
    			#address-cells = <1>;
    			#size-cells = <0>;
    
    			port@0 {
    				reg = <0>;
    
    				tpd12s015_in: endpoint {
    					remote-endpoint = <&hdmi_out>;
    				};
    			};
    
    			port@1 {
    				reg = <1>;
    
    				tpd12s015_out: endpoint {
    					remote-endpoint = <&hdmi_connector_in>;
    				};
    			};
    		};
    	};
    
    	btsco_mcasp3: btsco_mcasp3@0 {
    		#sound-dai-cells = <0>;
    		compatible = "delta,dfbmcs320-mcasp3";
    		status = "okay";
    	};
    
    	btsco_mcasp4: btsco_mcasp4@0 {
    		#sound-dai-cells = <0>;
    		compatible = "delta,dfbmcs320-mcasp4";
    		status = "okay";
    	};
    
    	snd0: sound@0 {
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "DRA7xx-EVM";
    #if 0
    		/* we do not have codec */
    		simple-audio-card,mclk-fs = <256>;
    #endif
    		simple-audio-card,widgets =
    			"Headphone", "Headphone Jack",
    			"Line", "Line Out",
    			"Microphone", "Mic Jack",
    			"Line", "Line In";
    		simple-audio-card,routing =
    			"Headphone Jack",       "HPLOUT",
    			"Headphone Jack",       "HPROUT",
    			"Line Out",		"LLOUT",
    			"Line Out",		"RLOUT",
    			"MIC3L",		"Mic Jack",
    			"MIC3R",		"Mic Jack",
    			"Mic Jack",		"Mic Bias",
    			"LINE1L",               "Line In",
    			"LINE1R",               "Line In";
    		status = "okay";
    
    		simple-audio-card,dai-link@0 {
    			format = "i2s";
    			bitclock-master = <&sound0_master>;
    			frame-master = <&sound0_master>;
    			bitclock-inversion;
    
    			sound0_master: cpu {
    				sound-dai = <&mcasp3>;
    				system-clock-frequency = <8192000>;
    			};
    
    			codec {
    				sound-dai = <&btsco_mcasp3>;
    			};
    		};
    
    		simple-audio-card,dai-link@1 {
    			format = "i2s";
    			bitclock-master = <&sound1_master>;
    			frame-master = <&sound1_master>;
    			bitclock-inversion;
    
    			sound1_master: cpu {
    				sound-dai = <&mcasp4>;
    				system-clock-frequency = <8192000>;
    			};
    
    			codec {
    				sound-dai = <&btsco_mcasp4>;
    			};
    		};
    	};
    
    #if 0
    	// GPIO5_8 is used for TDM pin
    	vmmcwl_fixed: fixedregulator-mmcwl {
    		compatible = "regulator-fixed";
    		regulator-name = "vmmcwl_fixed";
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    		gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
    		enable-active-high;
    	};
    #endif
    };
    
    &dra7_pmx_core {
    	mcasp3_pins: mcasp3_pins {
    		/* mcasp3 test with Carrier Board */
    		pinctrl-single,pins = <
    			0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* dedicate: B19_MCASP3_AXR0 */
    			0x330 (PIN_INPUT           | MUX_MODE0)	/* dedicate: C17_MCASP3_AXR1 */
    			/* clk master */
    			0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* B18_MCASP3_ACLKX*/
    			0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* F15_MCASP3_FSX */
    		>;
    	};
    
    	mcasp4_pins: mcasp4_pins {
    		/* mcasp4 test with Carrier Board */
    		pinctrl-single,pins = <
    			0x33c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* dedicate: G16_MCASP4_AXR0 */
    			/* clk master */
    			0x334 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* C18_MCASP4_ACLKX */
    			0x338 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* A21_MCASP4_FSX */
    		>;
    	};
    
            tps65917_pins_default: tps65917_pins_default {
                    pinctrl-single,pins = <
                            0x424 (PIN_INPUT_PULLUP | MUX_MODE1)    /* wakeup3.sys_nirq1 */
                    >;   
            };
    
    	mmc1_pins_default: mmc1_pins_default {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc2_pins_default: mmc2_pins_default {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc4_pins_default: mmc4_pins_default {
    		pinctrl-single,pins = <
    			0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
    			0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
    			0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
    			0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
    			0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
    			0x3fC (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
    		>;
    	};
    
    	dcan1_pins_default: dcan1_pins_default {
    		pinctrl-single,pins = <
    			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
    			0x418   (PULL_UP | MUX_MODE1)	/* wakeup0.dcan1_rx */
    		>;
    	};
    
    	dcan1_pins_sleep: dcan1_pins_sleep {
    		pinctrl-single,pins = <
    			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
    			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
    		>;
    	};
    
    #if 0
    	// GPIO5_8 function in TDM
    	wlan_pins: pinmux_wlan_pins {
    		pinctrl-single,pins = <
    			0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_ctsn.mmc4_clk */
    			0x3ec (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart1_rtsn.mmc4_cmd */
    			0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_rxd.mmc4_dat0 */
    			0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_txd.mmc4_dat1 */
    			0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_ctsn.mmc4_dat2 */
    			0x3fc (PIN_INPUT_PULLUP | MUX_MODE3)	/* uart2_rtsn.mmc4_dat3 */
    			0x2cc (PIN_OUTPUT | MUX_MODE14)		/* mcasp1_axr6.gpio5_8 - WLAN_EN */
    		>;
    	};
    #endif
    
    	wlirq_pins: pinmux_wlirq_pins {
    		pinctrl-single,pins = <
    			0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
    		>;
    	};
    };
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	tps65917: tps65917@58 {
    		compatible = "ti,tps65917";
    		reg = <0x58>;
    
    #if 0
    		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
    #else
                    pinctrl-names = "default";
                    pinctrl-0 = <&tps65917_pins_default>;
                    interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
                                            &dra7_pmx_core 0x424>;
                    interrupt-parent = <&gic>;
    #endif
    		interrupt-controller;
    		#interrupt-cells = <2>;
    
    		ti,system-power-controller;
    
    		tps65917_pmic {
    			compatible = "ti,tps65917-pmic";
    
    			tps65917_regulators: regulators {
    				smps1_reg: smps1 {
    					/* VDD_MPU */
    					regulator-name = "smps1";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps2_reg: smps2 {
    					/* VDD_CORE */
    					regulator-name = "smps2";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1150000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps3_reg: smps3 {
    					/* VDD_GPU IVA DSPEVE */
    					regulator-name = "smps3";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps4_reg: smps4 {
    					/* VDDS1V8 */
    					regulator-name = "smps4";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps5_reg: smps5 {
    					/* VDD_DDR */
    					regulator-name = "smps5";
    					regulator-min-microvolt = <1350000>;
    					regulator-max-microvolt = <1350000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo1_reg: ldo1 {
    					/* LDO1_OUT --> SDIO  */
    					regulator-name = "ldo1";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-always-on;
    					regulator-boot-on;
    					regulator-allow-bypass;
    				};
    
    				ldo3_reg: ldo3 {
    					/* VDDA_1V8_PHY */
    					regulator-name = "ldo3";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo5_reg: ldo5 {
    					/* VDDA_1V8_PLL */
    					regulator-name = "ldo5";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo4_reg: ldo4 {
    					/* VDDA_3V_USB: VDDA_USBHS33 */
    					regulator-name = "ldo4";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    				};
    			};
    		};
    
    		tps65917_power_button {
    			compatible = "ti,palmas-pwrbutton";
    			interrupt-parent = <&tps65917>;
    			interrupts = <1 IRQ_TYPE_NONE>;
    			wakeup-source;
    			ti,palmas-long-press-seconds = <6>;
    		};
    	};
    
    	pcf_lcd: gpio@20 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x20>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	pcf_gpio_21: gpio@21 {
    		status = "disabled";
    		compatible = "ti,pcf8575";
    		reg = <0x21>;
    		lines-initial-states = <0x1408>;
    		gpio-controller;
    		#gpio-cells = <2>;
    
    		interrupt-controller;
    		#interrupt-cells = <2>;
    	};
    
    	tlv320aic3106: tlv320aic3106@19 {
    		#sound-dai-cells = <0>;
    		compatible = "ti,tlv320aic3106";
    		reg = <0x19>;
    		adc-settle-ms = <40>;
    		ai3x-micbias-vg = <1>;		/* 2.0V */
    		status = "okay";
    
    		/* Regulators */
    		AVDD-supply = <&evm_3v3_sw>;
    		IOVDD-supply = <&evm_3v3_sw>;
    		DRVDD-supply = <&evm_3v3_sw>;
    		DVDD-supply = <&aic_dvdd>;
    	};
    };
    
    i2c_p3_exp: &i2c5 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	pcf_hdmi: pcf8575@26 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x26>;
    		gpio-controller;
    		#gpio-cells = <2>;
    		/*
    		 * initial state is used here to keep the mdio interface
    		 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
    		 * VIN2_S0 driven high otherwise Ethernet stops working
    		 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
    		 */
    		lines-initial-states = <0x0f2b>;
    
    		p1 {
    			/* vin6_sel_s0: high: VIN6, low: audio */
    			gpio-hog;
    			gpios = <1 GPIO_ACTIVE_HIGH>;
    			output-low;
    			line-name = "vin6_sel_s0";
    		};
    	};
    };
    
    &mcspi1 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {    
        spi-max-frequency = <16000000>;
        reg = <0>; 
            compatible = "rohm,dh2228fv";   
            status = "okay" ; 
            };   
            spidev@1
            {    
        spi-max-frequency = <16000000>;
        reg = <1>; 
            compatible = "rohm,dh2228fv";
            status = "okay" ; 
            };     
            spidev@3
            {    
        spi-max-frequency = <16000000>;
        reg = <3>; 
            compatible = "rohm,dh2228fv";   
            status = "okay" ; 
            };
    };
    
    &mcspi2 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {
        spi-max-frequency = <16000000>;
        reg = <0>;
            compatible = "rohm,dh2228fv";
            };
    };
    
    &mcspi3 {
            status = "okay";
            ti,pindir-d0-out-d1-in;
            spidev@0
            {
        spi-max-frequency = <16000000>;
        reg = <0>;
            compatible = "rohm,dh2228fv";
            };
    };
    
    &uart1 {
    	status = "okay";
    	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
    			      <&dra7_pmx_core 0x3e0>;
    };
    
    &uart3 {
    	status = "okay";
    };
    
    &elm {
    	status = "okay";
    };
    
    &gpmc {
    	/*
    	 * For the existing IOdelay configuration via U-Boot we don't
    	 * support NAND on dra72-evm. Keep it disabled. Enabling it
    	 * requires a different configuration by U-Boot.
    	 */
    	status = "disabled";
    	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
    	nand@0,0 {
    		/* To use NAND, DIP switch SW5 must be set like so:
    		 * SW5.1 (NAND_SELn) = ON (LOW)
    		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
    		 */
    		compatible = "ti,omap2-nand";
    		reg = <0 0 4>;          /* device IO registers */
    		interrupt-parent = <&gpmc>;
    		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
    			     <1 IRQ_TYPE_NONE>; /* termcount */
    		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */	/* device IO registers */
    		ti,nand-ecc-opt = "bch8";
    		ti,elm-id = <&elm>;
    		nand-bus-width = <16>;
    		gpmc,device-width = <2>;
    		gpmc,sync-clk-ps = <0>;
    		gpmc,cs-on-ns = <0>;
    		gpmc,cs-rd-off-ns = <80>;
    		gpmc,cs-wr-off-ns = <80>;
    		gpmc,adv-on-ns = <0>;
    		gpmc,adv-rd-off-ns = <60>;
    		gpmc,adv-wr-off-ns = <60>;
    		gpmc,we-on-ns = <10>;
    		gpmc,we-off-ns = <50>;
    		gpmc,oe-on-ns = <4>;
    		gpmc,oe-off-ns = <40>;
    		gpmc,access-ns = <40>;
    		gpmc,wr-access-ns = <80>;
    		gpmc,rd-cycle-ns = <80>;
    		gpmc,wr-cycle-ns = <80>;
    		gpmc,bus-turnaround-ns = <0>;
    		gpmc,cycle2cycle-delay-ns = <0>;
    		gpmc,clk-activation-ns = <0>;
    		gpmc,wait-monitoring-ns = <0>;
    		gpmc,wr-data-mux-bus-ns = <0>;
    		/* MTD partition table */
    		/* All SPL-* partitions are sized to minimal length
    		 * which can be independently programmable. For
    		 * NAND flash this is equal to size of erase-block */
    		#address-cells = <1>;
    		#size-cells = <1>;
    		partition@0 {
    			label = "NAND.SPL";
    			reg = <0x00000000 0x000020000>;
    		};
    		partition@1 {
    			label = "NAND.SPL.backup1";
    			reg = <0x00020000 0x00020000>;
    		};
    		partition@2 {
    			label = "NAND.SPL.backup2";
    			reg = <0x00040000 0x00020000>;
    		};
    		partition@3 {
    			label = "NAND.SPL.backup3";
    			reg = <0x00060000 0x00020000>;
    		};
    		partition@4 {
    			label = "NAND.u-boot-spl-os";
    			reg = <0x00080000 0x00040000>;
    		};
    		partition@5 {
    			label = "NAND.u-boot";
    			reg = <0x000c0000 0x00100000>;
    		};
    		partition@6 {
    			label = "NAND.u-boot-env";
    			reg = <0x001c0000 0x00020000>;
    		};
    		partition@7 {
    			label = "NAND.u-boot-env.backup1";
    			reg = <0x001e0000 0x00020000>;
    		};
    		partition@8 {
    			label = "NAND.kernel";
    			reg = <0x00200000 0x00800000>;
    		};
    		partition@9 {
    			label = "NAND.file-system";
    			reg = <0x00a00000 0x0f600000>;
    		};
    	};
    };
    
    &usb2_phy1 {
    	phy-supply = <&ldo4_reg>;
    };
    
    &usb2_phy2 {
    	phy-supply = <&ldo4_reg>;
    };
    
    &omap_dwc3_1 {
    //	extcon = <&extcon_usb1>;
    };
    
    &omap_dwc3_2 {
    //	extcon = <&extcon_usb2>;
    };
    
    &usb1 {
    	status = "ok";
    	dr_mode = "host";
    };
    
    &usb2 {
    	status = "ok";
    	dr_mode = "host";
    };
    
    &usb3 {
    	status = "disabled";
    };
    
    &mmc1 {
    	status = "okay";
    
    	vmmc-supply = <&evm_3v3_sw>;
    	vmmc_aux-supply = <&ldo1_reg>;
    	bus-width = <4>;
    	/*
    	 * SDCD signal is not being used here - using the fact that GPIO mode
    	 * is a viable alternative
    	 */
    	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
    	max-frequency = <192000000>;
    };
    
    &mmc2 {
    	/* SW5-3 in ON position */
    	status = "okay";
    
    	vmmc-supply = <&evm_3v3_sw>;
    	bus-width = <8>;
    	ti,non-removable;
    	max-frequency = <192000000>;
    };
    
    &mmc4 {
    #if 1
            status = "okay";
    
            bus-width = <4>; 
            pinctrl-names = "default";
            pinctrl-0 = <&mmc4_pins_default>;
    	vmmc-supply = <&evm_3v3_sw>;
    #else
    	status = "okay";
    	vmmc-supply = <&vmmcwl_fixed>;
    	bus-width = <4>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&wlan_pins &wlirq_pins>;
    	cap-power-off-card;
    	keep-power-in-suspend;
    	ti,non-removable;
    
    	#address-cells = <1>;
    	#size-cells = <0>;
    	wlcore: wlcore@0 {
    		compatible = "ti,wl1835";
    		reg = <2>;
    		interrupt-parent = <&gpio5>;
    		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    	};
    #endif
    };
    
    &mac {
    	status = "okay";
    };
    
    &dcan1 {
    	status = "ok";
    };
    
    &qspi {
    	status = "okay";
    
    	spi-max-frequency = <64000000>;
    	m25p80@0 {
    		compatible = "s25fl256s1";
    		spi-max-frequency = <64000000>;
    		reg = <0>;
    		spi-tx-bus-width = <1>;
    		spi-rx-bus-width = <4>;
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		/* MTD partition table.
    		 * The ROM checks the first four physical blocks
    		 * for a valid file to boot and the flash here is
    		 * 64KiB block size.
    		 */
    		partition@0 {
    			label = "QSPI.SPL";
    			reg = <0x00000000 0x000040000>;
    		};
    		partition@1 {
    			label = "QSPI.u-boot";
    			reg = <0x00040000 0x00100000>;
    		};
    		partition@2 {
    			label = "QSPI.u-boot-spl-os";
    			reg = <0x00140000 0x00080000>;
    		};
    		partition@3 {
    			label = "QSPI.u-boot-env";
    			reg = <0x001c0000 0x00010000>;
    		};
    		partition@4 {
    			label = "QSPI.u-boot-env.backup1";
    			reg = <0x001d0000 0x0010000>;
    		};
    		partition@5 {
    			label = "QSPI.kernel";
    			reg = <0x001e0000 0x0800000>;
    		};
    		partition@6 {
    			label = "QSPI.file-system";
    			reg = <0x009e0000 0x01620000>;
    		};
    	};
    };
    
    &hdmi {
    	status = "disabled";
    
    	port {
    		hdmi_out: endpoint {
    			remote-endpoint = <&tpd12s015_in>;
    		};
    	};
    };
    
    &atl {
    	assigned-clocks = <&abe_dpll_sys_clk_mux>,
    			  <&atl_gfclk_mux>,
    			  <&dpll_abe_ck>,
    			  <&dpll_abe_m2x2_ck>,
    			  <&atl_clkin1_ck>,
    			  <&atl_clkin2_ck>;
    	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
    #if 0
    	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
    			       <11289600>, <11289600>;
    #else
    	assigned-clock-rates = <0>, <0>, <122880000>, <245760000>,
    			       <8192000>, <8192000>;
    #endif
    
    #if 0
    	status = "okay";
    #else
    	status = "disabled";
    #endif
    
    	atl2 {
    		bws = <DRA7_ATL_WS_MCASP2_FSX>;
    		aws = <DRA7_ATL_WS_MCASP3_FSX>;
    	};
    };
    
    &mcasp3 {
    	#sound-dai-cells = <0>;
    	fck_parent = "atl_clkin2_ck";
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcasp3_pins>;
    
    	status = "okay";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		1 2 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    &mcasp4 {
    	#sound-dai-cells = <0>;
    	fck_parent = "atl_clkin2_ck";
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcasp4_pins>;
    
    	status = "okay";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		1 0 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    &mailbox5 {
    	status = "okay";
    	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
    		status = "okay";
    	};
    	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
    		status = "okay";
    	};
    };
    
    &mailbox6 {
    	status = "okay";
    	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
    		status = "okay";
    	};
    };
    
    &mmu0_dsp1 {
    	status = "okay";
    };
    
    &mmu1_dsp1 {
    	status = "okay";
    };
    
    &mmu_ipu1 {
    	status = "okay";
    };
    
    &mmu_ipu2 {
    	status = "okay";
    };
    
    &ipu2 {
    	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
    	timers = <&timer3>;
    	watchdog-timers = <&timer4>, <&timer9>;
    };
    
    &ipu1 {
    	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
    	timers = <&timer11>;
    	watchdog-timers = <&timer7>, <&timer8>;
    };
    
    &dsp1 {
    	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
    	timers = <&timer5>;
    	watchdog-timers = <&timer10>;
    };
    
    &oppdm_mpu {
    	vdd-supply = <&smps1_reg>;
    };
    
    &oppdm_core {
    	vdd-supply = <&smps2_reg>;
    };
    
    &oppdm_dspeve {
    	vdd-supply = <&smps3_reg>;
    };
    
    &oppdm_gpu {
    	vdd-supply = <&smps3_reg>;
    };
    
    &oppdm_ivahd {
    	vdd-supply = <&smps3_reg>;
    };
    

    4.2 CB DTS file

    4130.dra7-evm.dts.txt
    /*
     * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
     *
     * This program is free software; you can redistribute it and/or modify
     * it under the terms of the GNU General Public License version 2 as
     * published by the Free Software Foundation.
     */
    /dts-v1/;
    
    #include "dra74x.dtsi"
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/clk/ti-dra7-atl.h>
    #include <dt-bindings/pinmux/mux_dra7xx.h>
    
    / {
    	model = "TI DRA742 Louis 20170801 09:00";
    	compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
    	
    	version = "20161109" ;
    	
    	memory {
    		device_type = "memory";
    		//reg = <0x80000000 0x60000000>; /* 1536 MB */							
    		//reg = <0x80000000 0x80000000>; /* 2048 MB */
    		reg = <0x80000000 0x20000000>; /* 512 MB */
    	};
    
    
    	leds {
    		pinctrl-names = "default";
    		pinctrl-0 = <&user_leds_default>;
    
    		compatible = "gpio-leds";
    
    		led@1 {
    			label = "FPGA_EN";
    			gpios = <&gpio8 23 GPIO_ACTIVE_HIGH>;
    			linux,default-trigger = "none";
    			default-state = "on";
    		};
    	};
    
    	reserved_mem: reserved-memory {
    		#address-cells = <1>;
    		#size-cells = <1>;
    		ranges;
    
    		ipu2_cma_pool: ipu2_cma@95800000 {
    			compatible = "shared-dma-pool";
    			reg = <0x95800000 0x3800000>;
    			reusable;
    			status = "okay";
    		};
    
    		dsp1_cma_pool: dsp1_cma@99000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x99000000 0x4000000>;
    			reusable;
    			status = "okay";
    		};
    
    		ipu1_cma_pool: ipu1_cma@9d000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x9d000000 0x2000000>;
    			reusable;
    			status = "okay";
    		};
    
    		dsp2_cma_pool: dsp2_cma@9f000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x9f000000 0x800000>;
    			reusable;
    			status = "okay";
    		};
    	};
    
    	extcon_usb1: extcon_usb1 {
    		status = "ok";
    		compatible = "linux,extcon-usb-gpio";
    		//id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
    		id-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
    	};
    
    	extcon_usb2: extcon_usb2 {
    		status = "ok";
    		compatible = "linux,extcon-usb-gpio";
    		//id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
    		id-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
    	};
    
    	evm_3v3_sd: fixedregulator-sd {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sd";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	evm_3v3_sw: fixedregulator-evm_3v3_sw {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_3v3_sw";
    		vin-supply = <&sysen1>;
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    	};
    
    	aic_dvdd: fixedregulator-aic_dvdd {
    		/* TPS77018DBVT */
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd";
    		vin-supply = <&evm_3v3_sw>;
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    	};
    
    	vmmcwl_fixed: fixedregulator-mmcwl {
    		compatible = "regulator-fixed";
    		regulator-name = "vmmcwl_fixed";
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    		//gpio = <&gpio5 8 0>;	/* gpio5_8 */
    		startup-delay-us = <70000>;
    		enable-active-high;
    	};
    
    /*
    	kim {
    		compatible = "kim";
    		nshutdown_gpio = <132>;
    		dev_name = "/dev/ttyS2";
    		flow_cntrl = <1>;
    		baud_rate = <3686400>;
    	};
    
    	btwilink {
    		compatible = "btwilink";
    	};
    */
    	vtt_fixed: fixedregulator-vtt {
    		compatible = "regulator-fixed";
    		regulator-name = "vtt_fixed";
    		regulator-min-microvolt = <1350000>;
    		regulator-max-microvolt = <1350000>;
    		regulator-always-on;
    		regulator-boot-on;
    		enable-active-high;
    		vin-supply = <&sysen2>;
    		//gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
    	};
    
    	aliases {
    		display0 = &hdmi0;
    		sound0 = &snd0;
    		sound1 = &hdmi;
    	};
    
    	hdmi0: connector@1 {
    		compatible = "hdmi-connector";
    		label = "hdmi";
    
    		type = "a";
    
    		port {
    			hdmi_connector_in: endpoint {
    				remote-endpoint = <&tpd12s015_out>;
    			};
    		};
    	};
    
    	tpd12s015: encoder@1 {
    		compatible = "ti,dra7evm-tpd12s015";
    		status = "disabled";
    
    		pinctrl-names = "i2c", "ddc";
    		pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
    		pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
    
    		ddc-i2c-bus = <&i2c2>;
    		mcasp-gpio = <&mcasp8>;
    
    		gpios = <&pcf_hdmi 4 0>,	/* P4, CT CP HPD */
    			<&pcf_hdmi 5 0>,	/* P5, LS OE */
    			<&gpio7 12 0>;	/* gpio7_12/sp1_cs2, HPD */
    
    		ports {
    			#address-cells = <1>;
    			#size-cells = <0>;
    
    			port@0 {
    				reg = <0>;
    
    				tpd12s015_in: endpoint@0 {
    					remote-endpoint = <&hdmi_out>;
    				};
    			};
    
    			port@1 {
    				reg = <1>;
    
    				tpd12s015_out: endpoint@0 {
    					remote-endpoint = <&hdmi_connector_in>;
    				};
    			};
    		};
    	};
    
        ocp {
            gpu: gpu@0x56000000 {
                gpu0-voltdm = <&voltdm_gpu>;
            };
        };
    
    	btsco_mcasp3: btsco_mcasp3@0 {
    		#sound-dai-cells = <0>;
    		status = "okay";
    		compatible = "linux,bt-sco-audio-mcasp3";
    	};
    
    	btsco_mcasp4: btsco_mcasp4@0 {
    		#sound-dai-cells = <0>;
    		status = "okay";
    		compatible = "linux,bt-sco-audio-mcasp4";
    	};
    
            snd0: sound@0 {
                    compatible = "simple-audio-card";
                    simple-audio-card,name = "DRA7xx-EVM";
    #if 0
    		/* we do not have codec */
    		simple-audio-card,mclk-fs = <256>;
    #endif
                    simple-audio-card,widgets =
                            "Headphone", "Headphone Jack",
                            "Line", "Line Out",
                            "Microphone", "Mic Jack",
                            "Line", "Line In";
                    simple-audio-card,routing =
                            "Headphone Jack",       "HPLOUT",
                            "Headphone Jack",       "HPROUT",
                            "Line Out",             "LLOUT",
                            "Line Out",             "RLOUT",
                            "MIC3L",                "Mic Jack",
                            "MIC3R",                "Mic Jack",
                            "Mic Jack",             "Mic Bias",
                            "LINE1L",               "Line In",
                            "LINE1R",               "Line In";
    		status = "okay";
    
    		simple-audio-card,dai-link@0 {
    			format = "i2s";
    			bitclock-master = <&btsco_codec0>;
    			frame-master = <&btsco_codec0>;
    			bitclock-inversion;
    
    			cpu {
    				sound-dai = <&mcasp3>;
    				system-clock-frequency = <8192000>;
    			};
    
    			btsco_codec0: codec {
    				sound-dai = <&btsco_mcasp3>;
    			};
    		};
    
    #if 1
    		simple-audio-card,dai-link@1 {
    			format = "i2s";
    			bitclock-master = <&btsco_codec1>;
    			frame-master = <&btsco_codec1>;
    			bitclock-inversion;
    
    			cpu {
    				sound-dai = <&mcasp4>;
    				system-clock-frequency = <8192000>;
    			};
    
    			btsco_codec1: codec {
    				sound-dai = <&btsco_mcasp4>;
    			};
    		};
    #endif
            };
    };
    
    &dra7_pmx_core {
    
        // 20161109 For CB ver.F
    	cpsw_default: cpsw_default {
    		pinctrl-single,pins = <
    			// Slave 1 
    			
    			0x250 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_tclk.rgmii0_tclk W9 
    			0x254 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_tctl.rgmii0_tctl V9 
    			0x258 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td3.rgmii0_td3  V7 
    			0x25c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td2.rgmii0_td2  U7
    			0x260 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td1.rgmii0_td1 V6 
    			0x264 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	// rgmii0_td0.rgmii0_td0 U6 
    			0x268 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rmii0_rclk.rmii0_rclk U5 
    			0x26c (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rctl.rgmii0_rctl V5 
    			0x270 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd3.rgmii0_rd3 V4 
    			0x274 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd2.rgmii0_rd2 V3 
    			0x278 (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd1.rgmii0_rd1 Y2 
    			0x27c (PIN_INPUT_PULLDOWN | MUX_MODE0)	// rgmii0_rd0.rgmii0_rd0 W2 
    			
    			
    			// Slave 2 
    			0x198 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d12.rgmii1_tclk D5 
    			0x19c (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d13.rgmii1_tctl C2 
    			0x1a0 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d14.rgmii1_td3 C3 
    			0x1a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d15.rgmii1_td2 C4 
    			0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d16.rgmii1_td1 B2 
    			0x1ac (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	// vin2a_d17.rgmii1_td0 D6 
    			0x1b0 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d18.rgmii1_rclk C5 
    			0x1b4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d19.rgmii1_rctl A3 
    			0x1b8 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d20.rgmii1_rd3 B3 
    			0x1bc (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d21.rgmii1_rd2 B4 
    			0x1c0 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d22.rgmii1_rd1 B5 
    			0x1c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)	// vin2a_d23.rgmii1_rd0 A4
    		>;
    	};
    
    	
    	uart1_pins: pinmux_uart1_pins {
    		pinctrl-single,pins = <		
    
    			/* audio mcasp3 test with Adapt Board */
    			MCASP3_AXR0	(PIN_INPUT           | MUX_MODE0)	/* mcasp3_axr0, mode 0 */	// decidated	B19, 0x32C
    			MCASP3_AXR1	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr1, mode 0 */	// decidated	C17, 0x330
    			MCASP3_ACLKX	(PIN_INPUT           | MUX_MODE0)	/* mcasp3_aclkx */		//		B18, 0x324
    			MCASP3_FSX	(PIN_INPUT           | MUX_MODE0)	/* mcasp3_fsx */		//		F15, 0x328
    
    			/* audio mcasp4 test with Adapt Board */
    			MCASP4_ACLKX	(PIN_INPUT           | MUX_MODE0)	/* mcasp4_aclkx */	// decidated
    			MCASP4_FSX	(PIN_INPUT           | MUX_MODE0)	/* mcasp4_fsx */ 	// decidated  
          			MCASP4_AXR0	(PIN_INPUT           | MUX_MODE0)	/* mcasp4_axr0 */	// decidated 
    
    			UART1_RXD		(WAKEUP_EN | PIN_INPUT | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
    			UART1_TXD		(PIN_OUTPUT | MUX_MODE0)		/* uart1_txd.uart1_txd */		
    			UART1_CTSN	(PIN_OUTPUT | MUX_MODE0)			/* uart1_ctsn.uart1_ctsn */
    			UART1_RTSN	(PIN_INPUT | MUX_MODE0) 			/* uart1_rtsn.uart1_rtsn */
    
    			/* Can not do pin defines in I2C section */
    			/* Move all the I2C pin defines here */
    			// I2C1 controls
    			VIN2A_D0	(PIN_INPUT | MUX_MODE14)				 /* vin2a_d0.gpio4_1 */
    			VIN2A_D1	(PIN_INPUT | MUX_MODE14)				 /* vin2a_d1.gpio4_2 */	
    			// I2C4 controls
    			VIN1A_D7	(PIN_INPUT | MUX_MODE14)				 /* vin1a_d7.gpio3_11 */
    			VIN1A_D8	(PIN_INPUT | MUX_MODE14)				 /* vin1a_d8.gpio3_12 */
    			
    			//I2C4 PIN defines		
    			//MMC1_SDCD (PIN_INPUT | MUX_MODE4)  /* mmc1_sdcd.i2c4_sda -> 4 */
    			//MMC1_SDWP (PIN_INPUT | MUX_MODE4)  /* mmc1_sdwp.i2c4_scl -> 4 */
    			//I2C4 as GPIO		
    			MMC1_SDCD (PIN_INPUT | MUX_MODE14)  /* mmc1_sdcd.gpio?_?? */
    			MMC1_SDWP (PIN_INPUT | MUX_MODE14)  /* mmc1_sdwp.gpio?_?? */	
    
    			//I2C5 as GPIO for 7-segment display, Carrier Board hardware ver #F use i2c5
    			GPMC_A4 (PIN_INPUT | MUX_MODE7) /* gpmc_a4.i2c5_scl -> 7 */
    			GPMC_A5 (PIN_INPUT | MUX_MODE7) /* gpmc_a5.i2c5_sda -> 7 */
    
    			// POWINGING_SEQUENCE
    			// MD_12VPA_EN
    			GPMC_A10		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a10.gpio2_0 */
    			// MD_12VPB_EN
    			GPMC_A11		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a11.gpio2_1 */
    			// SOC_POWER_ON
    			GPMC_A12		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a12.gpio2_2 */
    #if 1       // 20161109 For CB ver.F			
    			// AB_VERSION
    			GPMC_A13		(PIN_INPUT | MUX_MODE14)		/* gpmc_a13.gpio2_3 */
    			GPMC_A14		(PIN_INPUT | MUX_MODE14)		/* gpmc_a14.gpio2_4 */
    			GPMC_A15		(PIN_INPUT | MUX_MODE14)		/* gpmc_a15.gpio2_5 */
    			GPMC_A16		(PIN_INPUT | MUX_MODE14)		/* gpmc_a16.gpio2_6 */
    
    			// CB_VERSION
    			GPMC_A13		(PIN_INPUT | MUX_MODE14)		/* gpmc_a13.gpio2_7 */
    			GPMC_A14		(PIN_INPUT | MUX_MODE14)		/* gpmc_a14.gpio2_8 */
    			GPMC_A15		(PIN_INPUT | MUX_MODE14)		/* gpmc_a15.gpio2_9 */
    			GPMC_A16		(PIN_INPUT | MUX_MODE14)		/* gpmc_a16.gpio2_10 */
    #endif
    							
    			// SOC_REST_EN
    			VIN1A_D2		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d2.gpio3_6 */
    
    			// BOOT MODE				
    			MMC3_DAT1		(PIN_INPUT | MUX_MODE14)		/* mmc3_dat1.gpio7_0 */
    			MMC3_DAT2		(PIN_INPUT | MUX_MODE14)		/* mmc3_dat2.gpio7_1 */	
    	
    			// DEBUG MESSAGE MUX CONTROL
    		  	VIN2A_DE0		(PIN_OUTPUT | MUX_MODE14)		/* vin2a_de0.gpio3_29  ==> 0x4A00_3558  ==> 0x1558 ==> 0x158 */	 
    
    		 	// LGA_SYSBOOT_1, _2, _3, _5
    		 	VIN1A_D21		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d21.gpio3_25	*/
    		 	VIN1A_D22		(PIN_OUTPUT | MUX_MODE14)		/* vin1a_d22.gpio3_26 */
    		 	USB2_DRVVBUS		(PIN_OUTPUT | MUX_MODE14)		/* usb2_drvvbus.gpio6_13 */
    		 	//GPMC_A25		(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a25.gpio2_15 */
    		 	
    		 	// SATA_PATH_SELECT
    		 	GPMC_A6			(PIN_OUTPUT | MUX_MODE14)		/* gpmc_a6.gpio1_28 */
                            // SATA_RST_N
                            GPIO6_14		(PIN_OUTPUT | MUX_MODE14)
    
    
    			// Carrier Board control Adapt Board INA226 chip x 5, only for iMX6, use i2c2, gpio5_2 & gpio5_3 both need in gpio input
    			MCASP1_AXR0 (PIN_INPUT | MUX_MODE14)	/* mcasp1_axr0.gpio5_2 -> 10 */
    			MCASP1_AXR1 (PIN_INPUT | MUX_MODE14)	/* mcasp1_axr1.gpio5_3 -> 10 */
    			
    			0x408	(PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
    			0x40c	(PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
    
    //=================================================================================							
    		>;
    	};
    	
    	user_leds_default: user_leds_default {
    		pinctrl-single,pins = <
    			0x238 (PIN_OUTPUT | MUX_MODE14)	/* vout1_d23.gpio8_23 A10 FPGA_EN */	
    		>;
    	};
    	
    	uart2_pins: pinmux_uart2_pins {
    		pinctrl-single,pins = <
    			UART2_RXD		(WAKEUP_EN | PIN_INPUT | MUX_MODE4)	/* uart2_rxd.uart2_rxd */
    			UART2_TXD		(PIN_OUTPUT | MUX_MODE4)		/* uart2_txd.uart2_txd */		
    		>;
    	};	
    	
    	uart3_pins: pinmux_uart3_pins {
    		pinctrl-single,pins = <
    			0x3f8 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* uart2_ctsn.uart3_rxd */
    			0x3fc (PIN_OUTPUT | MUX_MODE1)			/* uart2_rtsn.uart3_txd */			
    		>;
    	};
    
    //   Socket board
    
    //	uart3_pins: pinmux_uart3_pins {
    //		pinctrl-single,pins = <
    //			0x34c (PIN_INPUT_PULLUP | PIN_INPUT | MUX_MODE4)	/* mcasp5_axr0.uart3_rxd */
    //			0x350 (PIN_OUTPUT | MUX_MODE4)	/* mcasp5_axr1.uart3_txd */			
    //		>;
    //	};
    
    	uart5_pins: pinmux_uart5_pins {
    		pinctrl-single,pins = <
    			VOUT1_D0 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* vout1_d0.uart5_rxd */
    			VOUT1_D1 (PIN_OUTPUT | MUX_MODE2)						/* vout1_d1.uart5_txd */
    			VOUT1_D3 (PIN_OUTPUT | MUX_MODE14)					/* vout1_d3.gpio8_3 */
    			VOUT1_D4 (PIN_OUTPUT | MUX_MODE14)					/* vout1_d4.gpio8_4 */
    												
    		>;
    	};
    	
    	uart7_pins: pinmux_uart7_pins {
    		pinctrl-single,pins = <
    			VOUT1_D16 (WAKEUP_EN | PIN_INPUT | MUX_MODE2)	/* vout1_d16.uart7_rxd */
    			//VOUT1_D16 (PIN_OUTPUT | MUX_MODE14)							/* vout1_d16.gpio8_16 */
    			VOUT1_D17 (PIN_OUTPUT | MUX_MODE2)						/* vout1_d17.uart7_txd */		
    			//VOUT1_D17 (PIN_OUTPUT | MUX_MODE14)							/* vout1_d17.gpio8_17 */	
    		>;
    	};
    
    	davinci_mdio_pins_default: pinmux_davinci_mdio_pins_default {
    		pinctrl-single,pins = <
    			/* MDIO */
    				0x190	(	PIN_OUTPUT_PULLUP | MUX_MODE3 )				/* vin2a_d10.mdio_clk */
    				0x194 ( PIN_INPUT_PULLUP | MUX_MODE3 )				/* vin2a_d11.mkio_d */
    		>;
    	};
    
    
    	hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
    		pinctrl-single,pins = <
    			/* this pin is used as a GPIO via mcasp */
    			0x2fc	(PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
    		>;
    	};
    
    	hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
    		pinctrl-single,pins = <
    			0x408	(PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
    			0x40c	(PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
    		>;
    	};
    
    	hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
    		pinctrl-single,pins = <
    			0x408	(PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
    			0x40c	(PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
    		>;
    	};
    
    	dcan1_pins_default: dcan1_pins_default {
    		pinctrl-single,pins = <
    			0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* dcan1_tx */
    			0x418   (PULL_UP | MUX_MODE1)		/* wakeup0.dcan1_rx */
    		>;
    	};
    
    	dcan1_pins_sleep: dcan1_pins_sleep {
    		pinctrl-single,pins = <
    			0x3d0   (MUX_MODE15 | PULL_UP)	/* dcan1_tx.off */
    			0x418   (MUX_MODE15 | PULL_UP)	/* wakeup0.off */
    		>;
    	};
    
    	mmc1_pins_default: pinmux_mmc1_default_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
    			//0x36c (PIN_INPUT | MUX_MODE14)		/* mmc1sdcd.gpio187 */
    		>;
    	};
    
    	mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_hs: pinmux_mmc1_hs_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
    		pinctrl-single,pins = <
    			0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.clk */
    			0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.cmd */
    			0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.dat0 */
    			0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.dat1 */
    			0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.dat2 */
    			0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.dat3 */
    		>;
    	};
    
    	mmc2_pins_default: mmc2_pins_default {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc2_pins_hs: pinmux_mmc2_hs_pins {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    
    	mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
    		pinctrl-single,pins = <
    			0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
    			0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
    			0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
    			0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
    			0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
    			0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
    			0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
    			0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
    			0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
    			0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
    		>;
    	};
    };
    
    &dra7_iodelay_core {
    	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
    		pinctrl-single,pins = <
    			0x618 (A_DELAY(572) | G_DELAY(540))	/* CFG_MMC1_CLK_IN */
    			0x624 (A_DELAY(0) | G_DELAY(600))	/* CFG_MMC1_CMD_IN */
    			0x630 (A_DELAY(403) | G_DELAY(120))	/* CFG_MMC1_DAT0_IN */
    			0x63c (A_DELAY(23) | G_DELAY(60))	/* CFG_MMC1_DAT1_IN */
    			0x648 (A_DELAY(25) | G_DELAY(60))	/* CFG_MMC1_DAT2_IN */
    			0x654 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_IN */
    			0x620 (A_DELAY(1525) | G_DELAY(0))	/* CFG_MMC1_CLK_IN */
    			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
    			0x62c (A_DELAY(55) | G_DELAY(0))	/* CFG_MMC1_CMD_OUT */
    			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
    			0x638 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OUT */
    			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
    			0x644 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OUT */
    			0x64c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
    			0x650 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OUT */
    			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
    			0x65c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OUT */
    		>;
    	};
    
    	mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
    		pinctrl-single,pins = <
    			0x18c (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A19_IN */
    			0x1a4 (A_DELAY(265) | G_DELAY(360))	/* CFG_GPMC_A20_IN */
    			0x1b0 (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A21_IN */
    			0x1bc (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A22_IN */
    			0x1c8 (A_DELAY(287) | G_DELAY(420))	/* CFG_GPMC_A23_IN */
    			0x1d4 (A_DELAY(144) | G_DELAY(240))	/* CFG_GPMC_A24_IN */
    			0x1e0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_IN */
    			0x1ec (A_DELAY(0) | G_DELAY(120))	/* CFG_GPMC_A26_IN */
    			0x1f8 (A_DELAY(120) | G_DELAY(180))	/* CFG_GPMC_A27_IN */
    			0x360 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_IN */
    			0x190 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_OEN */
    			0x194 (A_DELAY(174) | G_DELAY(0))	/* CFG_GPMC_A19_OUT */
    			0x1a8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A20_OEN */
    			0x1ac (A_DELAY(168) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
    			0x1b4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A21_OEN */
    			0x1b8 (A_DELAY(136) | G_DELAY(0))	/* CFG_GPMC_A21_OUT */
    			0x1c0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OEN */
    			0x1c4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OUT */
    			0x1d0 (A_DELAY(879) | G_DELAY(0))	/* CFG_GPMC_A23_OUT */
    			0x1d8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OEN */
    			0x1dc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OUT */
    			0x1e4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OEN */
    			0x1e8 (A_DELAY(34) | G_DELAY(0))	/* CFG_GPMC_A25_OUT */
    			0x1f0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A26_OEN */
    			0x1f4 (A_DELAY(120) | G_DELAY(0))	/* CFG_GPMC_A26_OUT */
    			0x1fc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OEN */
    			0x200 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OUT */
    			0x364 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OEN */
    			0x368 (A_DELAY(11) | G_DELAY(0))	/* CFG_GPMC_CS1_OUT */
    		>;
    	};
    	
    	
    	i2c1_pins_default: pinmux_i2c1_pins {
    		pinctrl-single,pins = <
    			I2C1_SDA (PIN_OUTPUT_PULLUP | MUX_MODE0)  /* i2c1_sda.i2c1_sda */
    			I2C1_SCL (PIN_OUTPUT_PULLUP | MUX_MODE0)  /* i2c1_scl.i2c1_scl */
    		
    		>;
    	};	
    
    	i2c4_pins_default: pinmux_i2c4_pins {
    		pinctrl-single,pins = <
    			MMC1_SDCD (PIN_OUTPUT_PULLUP | MUX_MODE4)  /* mmc1_sdcd.i2c4_sda -> 4 */
    			MMC1_SDWP (PIN_OUTPUT_PULLUP | MUX_MODE4)  /* mmc1_sdwp.i2c4_scl -> 4 */
    
    		>;
    	};
    		
    	mcasp1_pins: mcasp1_pins {
    		pinctrl-single,pins = <
    			MCASP1_ACLKR 	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_0
          MCASP1_FSR    (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_1
    	    MCASP1_AXR3   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_5
    	    MCASP1_AXR4   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_6 
    	    MCASP1_AXR5   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_7 
    	    MCASP1_AXR6   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_8
    	    MCASP1_AXR7   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */	// gpio5_9
    		>;
    	};		
    
    	mcasp2_pins: mcasp2_pins {
    		pinctrl-single,pins = <
    			MCASP2_ACLKX  (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated
    			MCASP2_FSX    (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated  
    			MCASP2_AXR0   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated    
    			MCASP2_AXR1   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp0_aclkx */  // decidated    
    			MCASP2_AXR2   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DT_FM3_IBOC_IQ_DI */ 	//gpio6_8			
    			MCASP2_AXR3   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DT_FM3_IBOC_IQ_DQ */ 	//gpio6_9	 
    			MCASP2_AXR5   (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* DSP_FM_I2C_OUT */ 		//gpio6_7					
    		>;
    	};		
    
    		
    	mcasp3_pins: mcasp3_pins {
    		/* slave */
    		pinctrl-single,pins = <
    			/* audio mcasp3 test with Adapt Board */
    			MCASP3_ACLKX	(PIN_INPUT           | MUX_MODE0)	/* mcasp3_aclkx */			// gpio5_13			B18, 0x324
    			MCASP3_FSX	(PIN_INPUT           | MUX_MODE0)	/* mcasp3_fsx */			// gpio5_14			F15, 0x328
    			MCASP3_AXR0	(PIN_INPUT           | MUX_MODE0)	/* mcasp3_axr0, mode 0 */		// decidated			B19, 0x32C
    			MCASP3_AXR1	(PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mcasp3_axr1, mode 0 */		// decidated			C17, 0x330
    		>;
    	};
    	
    	mcasp4_pins: mcasp4_pins {
    		/* slave */
    		pinctrl-single,pins = <
    			/* audio mcasp4 test with Adapt Board */
    			MCASP4_ACLKX	(PIN_INPUT           | MUX_MODE0)	/* mcasp4_aclkx */	// decidated
    			MCASP4_FSX	(PIN_INPUT           | MUX_MODE0)	/* mcasp4_fsx */ 	// decidated  
          			MCASP4_AXR0	(PIN_INPUT           | MUX_MODE0)	/* mcasp4_axr0 */	// decidated 
    		>;
    	};			
    
    		
    };
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    
    	tps659038: tps659038@58 {
    		compatible = "ti,tps659038";
    		reg = <0x58>;
    
    		tps659038_pmic {
    			compatible = "ti,tps659038-pmic";
    
    			regulators {
    			 /*
    				smps123_reg: smps123 {
    					// VDD_MPU
    					regulator-name = "smps123";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    			  */
    
    				smps12_reg: smps12 {
    					/* VDD_MPU */
    					regulator-name = "smps12";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    				
    				smps3_reg: smps3 {
    					/* VDD_DDR */
    					regulator-name = "smps3";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps45_reg: smps45 {
    					/* VDD_DSPEVE */
    					regulator-name = "smps45";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1150000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps6_reg: smps6 {
    					/* VDD_GPU - over VDD_SMPS6 */
    					regulator-name = "smps6";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps7_reg: smps7 {
    					/* CORE_VDD */
    					regulator-name = "smps7";
    					regulator-min-microvolt = <850000>;
    					regulator-max-microvolt = <1060000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				smps8_reg: smps8 {
    					/* VDD_IVAHD */
    					regulator-name = "smps8";
    					regulator-min-microvolt = < 850000>;
    					regulator-max-microvolt = <1250000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				smps9_reg: smps9 {
    					/* VDDS1V8 */
    					regulator-name = "smps9";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo1_reg: ldo1 {
    					/* LDO1_OUT --> SDIO  */
    					regulator-name = "ldo1";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo2_reg: ldo2 {
    					/* VDD_RTCIO */
    					/* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
    					regulator-name = "ldo2";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldo3_reg: ldo3 {
    					/* VDDA_1V8_PHY */
    					regulator-name = "ldo3";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldo9_reg: ldo9 {
    					/* VDD_RTC */
    					regulator-name = "ldo9";
    					regulator-min-microvolt = <1050000>;
    					regulator-max-microvolt = <1050000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				ldoln_reg: ldoln {
    					/* VDDA_1V8_PLL */
    					regulator-name = "ldoln";
    					regulator-min-microvolt = <1800000>;
    					regulator-max-microvolt = <1800000>;
    					regulator-always-on;
    					regulator-boot-on;
    				};
    
    				ldousb_reg: ldousb {
    					/* VDDA_3V_USB: VDDA_USBHS33 */
    					regulator-name = "ldousb";
    					regulator-min-microvolt = <3300000>;
    					regulator-max-microvolt = <3300000>;
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				/* REGEN1 is unused */
    				regen1: regen1 {
    					/* Needed for PMIC internal resources */
    					regulator-name = "regen1";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    
    				regen2: regen2 {
    					/* Needed for PMIC internal resources */
    					regulator-name = "regen2";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				/* REGEN3 is unused */
    
    				sysen1: sysen1 {
    					/* PMIC_REGEN_3V3 */
    					regulator-name = "sysen1";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    
    				sysen2: sysen2 {
    					/* PMIC_REGEN_DDR */
    					regulator-name = "sysen2";
    					regulator-boot-on;
    					regulator-always-on;
    				};
    			};
    		};
    	};
    
    	pcf_lcd: gpio@20 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x20>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	pcf_gpio_21: gpio@21 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x21>;
    		lines-initial-states = <0x1408>;
    		gpio-controller;
    		#gpio-cells = <2>;
    		interrupt-parent = <&gpio6>;
    		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
    		interrupt-controller;
    		#interrupt-cells = <2>;
    	};
    
    
    	tlv320aic3106: tlv320aic3106@18 {
    		status = "disabled";
    		compatible = "ti,tlv320aic3106";
    		reg = <0x18>;
    		adc-settle-ms = <40>;
    		ai3x-micbias-vg = <1>;		/* 2.0V */
    		//status = "okay";
    
    		/* Regulators */
    		AVDD-supply = <&evm_3v3_sw>;
    		IOVDD-supply = <&evm_3v3_sw>;
    		DRVDD-supply = <&evm_3v3_sw>;
    		DVDD-supply = <&aic_dvdd>;
    	};
    };
    
    i2c_p3_exp: &i2c2 {
    	status = "disabled";
    	clock-frequency = <400000>;
    
    	pcf_hdmi: gpio@26 {
    		status = "disabled";
    		compatible = "nxp,pcf8575";
    		reg = <0x26>;
    		lines-initial-states = <0xffeb>;
    		gpio-controller;
    		#gpio-cells = <2>;
    	};
    
    	ov10633@37 {
    		compatible = "ovti,ov10633";
    		reg = <0x37>;
    		status = "disabled";
    		mux-gpios = <&pcf_hdmi 3	GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
    		port {
    			onboardLI: endpoint {
    				remote-endpoint = <&vin1a>;
    				hsync-active = <1>;
    				vsync-active = <1>;
    				pclk-sample = <0>;
    			};
    		};
    	};
    };
    
    &i2c2 {
    	status = "okay";
    	clock-frequency = <400000>;
    };
    
    &i2c3 {
    	status = "disabled";
    	clock-frequency = <3400000>;
    };
    
    &i2c4 {
    	status = "disabled";
    	clock-frequency = <400000>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&i2c4_pins_default>;	
    };
    
    
    &i2c5 {
    	status = "okay";
    	clock-frequency = <400000>;
    };
    
    &mcspi1 {
    	//status = "okay";
    	status = "disabled";
    };
    
    &mcspi2 {
    	//status = "okay";
    	status = "disabled";
    };
    
    &uart1 {
    	status = "okay";
    	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
    			       &dra7_pmx_core 0x3e0>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart1_pins>;
    };
    
    &uart2 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart2_pins>;		
    };
    
    /*
    * &uart3 {
    *	status = "okay";
    *	gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
    * };
    */
    
    &uart3 {
    	status = "okay";
    	//gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart3_pins>;
    };
    
    &uart5 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart5_pins>;
    };
    
    &uart7 {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart7_pins>;
    };
    
    
    &mmc1 {
    	status = "okay";
    	pbias-supply = <&pbias_mmc_reg>;
    	vmmc-supply = <&evm_3v3_sd>;
    	vmmc_aux-supply = <&ldo1_reg>;
    	bus-width = <4>;
    	/*
    	 * SDCD signal is not being used here - using the fact that GPIO mode
    	 * is always hardwired.
    	 */
    	/* cd-gpios = <&gpio6 27 0>; */
    	ti,non-removable;
    	pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
    	pinctrl-0 = <&mmc1_pins_default>;
    	pinctrl-1 = <&mmc1_pins_hs>;
    	pinctrl-2 = <&mmc1_pins_sdr12>;
    	pinctrl-3 = <&mmc1_pins_sdr25>;
    	pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
    	sd-uhs-ddr50;
    	sd-uhs-sdr25;
    	sd-uhs-sdr12;
    };
    
    
    &mmc2 {
    	status = "disabled";
    	//status = "okay";
    	vmmc-supply = <&evm_3v3_sw>;
    	bus-width = <8>;
    	pinctrl-names = "default", "hs", "ddr_3_3v";
    	pinctrl-0 = <&mmc2_pins_default>;
    	pinctrl-1 = <&mmc2_pins_hs>;
    	pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
    	mmc-ddr-1_8v;
    };
    
    &mmc4 {
    	//status = "okay";
    	status = "disabled";
    	vmmc-supply = <&vmmcwl_fixed>;
    	bus-width = <4>;
    	cap-power-off-card;
    	keep-power-in-suspend;
    	ti,non-removable;
    
    	#address-cells = <1>;
    	#size-cells = <0>;
    	wlcore: wlcore@0 {
    		compatible = "ti,wlcore";
    		reg = <2>;
    		interrupt-parent = <&gpio5>;
    		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
    	};
    };
    
    &cpu0 {
    	cpu0-voltdm = <&voltdm_mpu>;
    	voltage-tolerance = <1>;
    };
    
    &voltdm_mpu {
    	// OTP 82
    	//vdd-supply = <&smps123_reg>;
    	
    	// OTP60
    	vdd-supply = <&smps12_reg>;	
    };
    
    &voltdm_dspeve {
    	vdd-supply = <&smps45_reg>;
    };
    
    &voltdm_gpu {
    	vdd-supply = <&smps6_reg>;
    };
    
    &voltdm_ivahd {
    	vdd-supply = <&smps8_reg>;
    };
    
    &voltdm_core {
    	vdd-supply = <&smps7_reg>;
    };
    
    &qspi {
    	status = "okay";
    
    	spi-max-frequency = <48000000>;
    	m25p80@0 {
    		status = "disabled";
    		compatible = "s25fl256s1";
    		spi-max-frequency = <48000000>;
    		reg = <0>;
    		spi-tx-bus-width = <1>;
    		spi-rx-bus-width = <4>;
    		spi-cpol;
    		spi-cpha;
    		#address-cells = <1>;
    		#size-cells = <1>;
    
    		/* MTD partition table.
    		 * The ROM checks the first four physical blocks
    		 * for a valid file to boot and the flash here is
    		 * 64KiB block size.
    		 */
    		partition@0 {
    			label = "QSPI.SPL";
    			reg = <0x00000000 0x000010000>;
    		};
    		partition@1 {
    			label = "QSPI.SPL.backup1";
    			reg = <0x00010000 0x00010000>;
    		};
    		partition@2 {
    			label = "QSPI.SPL.backup2";
    			reg = <0x00020000 0x00010000>;
    		};
    		partition@3 {
    			label = "QSPI.SPL.backup3";
    			reg = <0x00030000 0x00010000>;
    		};
    		partition@4 {
    			label = "QSPI.u-boot";
    			reg = <0x00040000 0x00100000>;
    		};
    		partition@5 {
    			label = "QSPI.u-boot-spl-os";
    			reg = <0x00140000 0x00080000>;
    		};
    		partition@6 {
    			label = "QSPI.u-boot-env";
    			reg = <0x001c0000 0x00010000>;
    		};
    		partition@7 {
    			label = "QSPI.u-boot-env.backup1";
    			reg = <0x001d0000 0x0010000>;
    		};
    		partition@8 {
    			label = "QSPI.kernel";
    			reg = <0x001e0000 0x0800000>;
    		};
    		partition@9 {
    			label = "QSPI.file-system";
    			reg = <0x009e0000 0x01620000>;
    		};
    	};
    };
    
    &omap_dwc3_1 {
    		status = "ok";
    	extcon = <&extcon_usb1>;
    };
    
    &omap_dwc3_2 {
    		status = "ok";
    	extcon = <&extcon_usb2>;
    };
    
    &usb1 {
    dr_mode = "otg" ;
    };
    
    &usb2 {
    dr_mode = "otg" ;
    };
    
    
    &mac {
    	pinctrl-names = "default";
        pinctrl-0 = <&cpsw_default>;
    	status = "okay";
    	dual_emac;
    	ti,no-idle;
    };
    
    &davinci_mdio {
    	pinctrl-names = "default";
    	pinctrl-0 = <&davinci_mdio_pins_default>;
    };
    
    &cpsw_emac0 {
    	phy_id = <&davinci_mdio>, <0>;
    	phy-mode = "rgmii";
    	dual_emac_res_vlan = <1>;
    };
    
    &cpsw_emac1 {
    	phy_id = <&davinci_mdio>, <21>;
    	phy-mode = "rgmii";
    	dual_emac_res_vlan = <2>;
    };
    
    
    &elm {
    	status = "okay";
    };
    
    &gpmc {
    	status = "disabled";
    	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
    	nand@0,0 {
    		reg = <0 0 4>;		/* device IO registers */
    		ti,nand-ecc-opt = "bch8";
    		ti,elm-id = <&elm>;
    		nand-bus-width = <16>;
    		gpmc,device-width = <2>;
    		gpmc,sync-clk-ps = <0>;
    		gpmc,cs-on-ns = <0>;
    		gpmc,cs-rd-off-ns = <80>;
    		gpmc,cs-wr-off-ns = <80>;
    		gpmc,adv-on-ns = <0>;
    		gpmc,adv-rd-off-ns = <60>;
    		gpmc,adv-wr-off-ns = <60>;
    		gpmc,we-on-ns = <10>;
    		gpmc,we-off-ns = <50>;
    		gpmc,oe-on-ns = <4>;
    		gpmc,oe-off-ns = <40>;
    		gpmc,access-ns = <40>;
    		gpmc,wr-access-ns = <80>;
    		gpmc,rd-cycle-ns = <80>;
    		gpmc,wr-cycle-ns = <80>;
    		gpmc,bus-turnaround-ns = <0>;
    		gpmc,cycle2cycle-delay-ns = <0>;
    		gpmc,clk-activation-ns = <0>;
    		gpmc,wait-monitoring-ns = <0>;
    		gpmc,wr-data-mux-bus-ns = <0>;
    		/* MTD partition table */
    		/* All SPL-* partitions are sized to minimal length
    		 * which can be independently programmable. For
    		 * NAND flash this is equal to size of erase-block */
    		#address-cells = <1>;
    		#size-cells = <1>;
    		partition@0 {
    			label = "NAND.SPL";
    			reg = <0x00000000 0x000020000>;
    		};
    		partition@1 {
    			label = "NAND.SPL.backup1";
    			reg = <0x00020000 0x00020000>;
    		};
    		partition@2 {
    			label = "NAND.SPL.backup2";
    			reg = <0x00040000 0x00020000>;
    		};
    		partition@3 {
    			label = "NAND.SPL.backup3";
    			reg = <0x00060000 0x00020000>;
    		};
    		partition@4 {
    			label = "NAND.u-boot-spl-os";
    			reg = <0x00080000 0x00040000>;
    		};
    		partition@5 {
    			label = "NAND.u-boot";
    			reg = <0x000c0000 0x00100000>;
    		};
    		partition@6 {
    			label = "NAND.u-boot-env";
    			reg = <0x001c0000 0x00020000>;
    		};
    		partition@7 {
    			label = "NAND.u-boot-env.backup1";
    			reg = <0x001e0000 0x00020000>;
    		};
    		partition@8 {
    			label = "NAND.kernel";
    			reg = <0x00200000 0x00800000>;
    		};
    		partition@9 {
    			label = "NAND.file-system";
    			reg = <0x00a00000 0x0f600000>;
    		};
    	};
    };
    
    &gpio2 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*	
    	gpio2_0 {
    		gpio-hog;
    		gpios = < 0 0 >;
    		output-high;
    		line-name = "MD_12VPA_EN";
    	};
    
    	gpio2_1 {
    		gpio-hog;
    		gpios = < 1 0 >;
    		output-high;
    		line-name = "MD_12VPB_EN";
    	};
    	
    	gpio2_2 {
    		gpio-hog;
    		gpios = < 2 0 >;
    		output-high;
    		line-name = "SOC_POWER_ON";
    	};
    */	
    };
    
    &gpio3 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*
    	gpio3_6 {
    		gpio-hog;
    		gpios = < 6 0 >;
    		output-high;
    		line-name = "SOC_RESET_IN";
    	};
    	
    	gpio3_29 {
    		gpio-hog;
    		gpios = < 29 0 >;
    		output-high;
    		line-name = "AB_DEBUG_MUX_AB_USB";
    	};
    */	
    };
    
    &gpio7 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*	
    	gpio7_0 {
    		gpio-hog;
    		gpios = < 0 0 >;
    		output-high;
    		line-name = "BOOT_MODE0";	
    	};	
    
    	gpio7_1 {
    		gpio-hog;
    		gpios = < 1 0 >;
    		output-low;
    		line-name = "BOOT_MODE1";
    	};
    */	
    };
    
    &gpio8 {
    	ti,no-reset-on-init;
    	ti,no-idle-on-init;
    /*
    	gpio8_9 {
    		gpio-hog;
    		gpios = < 9 0 >;
    		output-high;
    		line-name = "FPGA_RST_N";
    	};
    */
    };
    
    &dss {
    	//status = "ok";
    	status = "disabled";
    	vdda_video-supply = <&ldoln_reg>;
    };
    
    &hdmi {
    	//status = "ok";
    	status = "disabled";
    	vdda-supply = <&ldo3_reg>;
    
    	port {
    		hdmi_out: endpoint {
    			remote-endpoint = <&tpd12s015_in>;
    		};
    	};
    };
    
    &dcan1 {
    	//status = "ok";
    	status = "disabled";
    	pinctrl-names = "default", "sleep";
    	pinctrl-0 = <&dcan1_pins_default>;
    	pinctrl-1 = <&dcan1_pins_sleep>;
    };
    
    &mailbox5 {
    	status = "okay";
    	mbox_ipu1_legacy: mbox_ipu1_legacy {
    		status = "okay";
    	};
    	mbox_dsp1_legacy: mbox_dsp1_legacy {
    		status = "okay";
    	};
    };
    
    &mailbox6 {
    	status = "okay";
    	mbox_ipu2_legacy: mbox_ipu2_legacy {
    		status = "okay";
    	};
    	mbox_dsp2_legacy: mbox_dsp2_legacy {
    		status = "okay";
    	};
    };
    
    &mmu0_dsp1 {
    	status = "okay";
    };
    
    &mmu1_dsp1 {
    	status = "okay";
    };
    
    &mmu0_dsp2 {
    	status = "okay";
    };
    
    &mmu1_dsp2 {
    	status = "okay";
    };
    
    &mmu_ipu1 {
    	status = "okay";
    };
    
    &mmu_ipu2 {
    	status = "okay";
    };
    
    &ipu2 {
    	status = "okay";
    	memory-region = <&ipu2_cma_pool>;
    	mboxes = <&mailbox6 &mbox_ipu2_legacy>;
    	timers = <&timer3>;
    	watchdog-timers = <&timer4>, <&timer9>;
    };
    
    &ipu1 {
    	status = "okay";
    	memory-region = <&ipu1_cma_pool>;
    	mboxes = <&mailbox5 &mbox_ipu1_legacy>;
    	timers = <&timer11>;
    	watchdog-timers = <&timer7>, <&timer8>;
    };
    
    &dsp1 {
    	status = "okay";
    	memory-region = <&dsp1_cma_pool>;
    	mboxes = <&mailbox5 &mbox_dsp1_legacy>;
    	timers = <&timer5>;
    	watchdog-timers = <&timer10>;
    };
    
    &dsp2 {
    	status = "okay";
    	memory-region = <&dsp2_cma_pool>;
    	mboxes = <&mailbox6 &mbox_dsp2_legacy>;
    	timers = <&timer6>;
    };
    
    &atl {
    	status = "okay";
    
    	atl2 {
    		bws = <DRA7_ATL_WS_MCASP2_FSX>;
    		aws = <DRA7_ATL_WS_MCASP3_FSX>;
    	};
    };
    
    // LOUIS ADD
    &mcasp1 {
    
    	//pinctrl-names = "default";
    	//pinctrl-0 = <&mcasp1_pins>;
    		
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 16 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		0 0 0 1  1 1 2 2
    		0 0 0 0  0 0 0 0
    	>;
    	tx-num-evt = <8>;			// fifo event level
    	rx-num-evt = <8>;
    };
    
    // LOUIS ADD
    &mcasp2 {
    
    	//pinctrl-names = "default";
    	//pinctrl-0 = <&mcasp2_pins>;
    		
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 16 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 2 1  0 1 0 0
    		0 0 0 0  0 0 0 0
    	>;
    	tx-num-evt = <8>;			// fifo event level
    	rx-num-evt = <8>;
    };
    
    &mcasp3 {
    	#sound-dai-cells = <0>;
    	fck_parent = "atl_clkin2_ck";
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcasp3_pins>;
    
    	status = "okay";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    // LOUIS ADD
    &mcasp4 {
    	#sound-dai-cells = <0>;
    	fck_parent = "atl_clkin2_ck";
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&mcasp4_pins>;
    
    	status = "okay";
    
    	op-mode = <0>;          /* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 0 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    
    &mcasp7 {
    	#sound-dai-cells = <0>;
    
    	//status = "okay";
    	status = "disabled";
    
    	op-mode = <0>;  /* MCASP_IIS_MODE */
    	tdm-slots = <4>;
    	/* 4 serializer */
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    		2 1 0 0
    	>;
    	tx-num-evt = <8>;
    	rx-num-evt = <8>;
    };
    
    &mcasp8 {
    	/* not used for audio. only the AXR2 pin is used as GPIO */
    	status = "disabled";
    };
    
    &usb2_phy1 {
    	phy-supply = <&ldousb_reg>;
    };
    
    &usb2_phy2 {
    	phy-supply = <&ldousb_reg>;
    };
    
    &vip1 {
    	status = "okay";
    };
    
    video_in: &vin1a {
    	//status = "okay";
    	status = "disabled";
    	endpoint@0 {
    		slave-mode;
    		remote-endpoint = <&onboardLI>;
    	};
    };
    
    #include "dra7xx-jamr3.dtsi"
    
    //
    //&tvp_5158{
    //	mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>,	/*CAM_FPD_MUX_S0*/
    //			<&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>;	/*SEL_TVP_FPD*/
    //};
    

    4.3 CB kernel panic log

    2017_08_03_CB_mcasp4_kernel_panic.txt
    U-Boot SPL 2014.07 (Aug 02 2017 - 18:05:53)
    DRA752-GP ES1.1
    before do_io_settings
    before prcm_init
            |-before enable_basic_clocks
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
    Enable clock module - 4a008728
    Enable clock module - 4a008b30
    Enable clock module - 4a008b38
    Enable clock module - 4a008d20
    Enable clock module - 4ae07838
    Enable clock module - 4a009760
    Enable clock module - 4a009768
    Enable clock module - 4a009770
    Enable clock module - 4a009778
    Enable clock module - 4a009780
    Enable clock module - 4a009810
    Enable clock module - 4a009818
    Enable clock module - 4a008778
    Enable clock module - 4a008780
    Enable clock module - 4ae07840
    Enable clock module - 4a009328
    Enable clock module - 4a009330
    Enable clock module - 4a009738
    Enable clock module - 4ae07830
    Enable clock module - 4a009850
    Enable clock module - 4a0097a0
    Enable clock module - 4a0093d0
    Enable clock module - 4a009838
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
            |-before timer_init
            |-before scale_vcores
                    |-before vcores->core
    optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1030, using efuse value 970
                    |-before core
    do_scale_vcore: volt - 970 offset_code - 0x35
                    |-before recalibrate_iodelay
    KEEP 6_30(ETH_SEL) input
    switch to NVA_SDIO (6_29 input).....
    switch to HDMI_I2C_SEL (6_12 input).....
    Power off LGA Board....
                            |-before __recalibrate_iodelay
                                    |-before calibrate_iodelay
                                    |-before isolate_io
                                            |- isolate = 1
                                            |-  wait_on_value1CBBBBB�Kwait_on_value2
    IODELAY: IO delay recalibration successfully completed
                    |-before vcores->mpu
    optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=1090, using efuse value 1010
                    |-before mpu
    do_scale_vcore: volt - 1010 offset_code - 0x39
                    |-before abb_setup
                    |-before mm
                    |-before mm
                    |-before gpu
    optimize_vcore_voltage:efuse 0x4a003b10 bits=16 Vnom=1250, using efuse value 1050
                    |-before gpu
    do_scale_vcore: volt - 1050 offset_code - 0x3d
                    |-before eve
    optimize_vcore_voltage:efuse 0x4a0025e0 bits=16 Vnom=1060, using efuse value 965
                    |-before eve
    do_scale_vcore: volt - 965 offset_code - 0x35
                    |-before iva
    optimize_vcore_voltage:efuse 0x4a0025cc bits=16 Vnom=1060, using efuse value 979
                    |-before iva
    do_scale_vcore: volt - 979 offset_code - 0x36
     |-before setup_dplls
    setup_dplls
    
     core Dpll locked, but not for ideal M = 277,N = 4 values, current values are M = 1330,N= 23
     before core[4a005120] Dpll wait_for_lock
    Core DPLL configured
    
     per Dpll locked, but not for ideal M = 20,N = 0 values, current values are M = 1280,N= ��j�I��KW$�Y?MX8140] Dpll wait_for_lock
    PER DPLL locked
    
     mpu Dpll locked, but not for ideal M = 625,N = 11 values, current values are M = 1470,N= 23
     before mpu[4a005160] Dpll wait_for_lock
    MPU DPLL locked
    
     before usb[4a008180] Dpll wait_for_lock
    
     before ddr[4a005210] Dpll wait_for_lock
    
     before gmac[4a0052a8] Dpll wait_for_lock
     |-before setup_warmreset_time
    before board_early_init_f
    before sdram_init
    >>sdram_init()
    in_sdram = 0
    >>do_sdram_init() 4c000000
    <<do_sdram_init() 4c000000
     size_prog = 20000000
    base=80000000 , maxsize=20000000 , cnt=8000000
    i=27
    get_ram_size() successful<<sdram_init()
    spl_mmc_load_image
    reading dra7-evm.dtb
    spl_load_image_fat_os: error reading image dra7-evm.dtb, err - -1
    reading u-boot.img
    reading u-boot.img
    before init_omap_revision
    before hw_data_init
    before watchdog_init
    before set_mux_conf_regs
    before prcm_init
    
    
    U-Boot 2014.07 (Aug 02 2017 - 18:05:53)
    
    CPU  : DRA752-GP ES1.1
    Board: DRA7xx
    I2C:   ready
    DRAM:  >>sdram_init()
    512 MiB
    NAND:  0 MiB
    MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
    *** Error - No Valid Environment Area found
    *** Warning - bad CRC, using default environment
    
    serial# not set, setting...
    SATA link 0 timeout.
    AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
    flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
    scanning bus for devices...
    Found 0 device(s).
    SCSI:  Net:   cpsw
    Hit any key to stop autoboot:  0
    U-Boot#
    U-Boot#
    U-Boot#
    U-Boot#
    U-Boot# pwr_on_j6_sd
    Turn on SATA
    SATA SEL
    Turn on ULPI
    Turn on PCIE
    Turn the 6165 and 1512 on.....
    U-Boot# run boot_cb
    ==== This is CB Ver.F =====
    switch to partitions #0, OK
    mmc0 is current device
    SD/MMC found on device 0
    reading uEnv.txt
    221 bytes read in 3 ms (71.3 KiB/s)
    Loaded environment from uEnv.txt
    Importing environment from mmc0 ...
    5487032 bytes read in 283 ms (18.5 MiB/s)
    102055 bytes read in 27 ms (3.6 MiB/s)
    Booting from mmc0 ...
    Kernel image @ 0x82000000 [ 0x000000 - 0x53b9b8 ]
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffe4000, end 8ffffea6 ... OK
    
    Starting kernel ...
    
    
    Starting kernel 4
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 3.14.49 (root@louis-VirtualBox) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #65 SMP PREEMPT Thu Aug 3 14:50:23 CST 2017
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] Machine model: TI DRA742 Louis 20170801 09:00
    [    0.000000] Reserved memory: created CMA memory pool at 0x95800000, size 56 MiB
    [    0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 64 MiB
    [    0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9d000000, size 32 MiB
    [    0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9f000000, size 8 MiB
    [    0.000000] Reserved memory: initialized node dsp2_cma@9f000000, compatible id shared-dma-pool
    [    0.000000] cma: CMA: reserved 64 MiB at 91000000
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] DRA752 ES1.1
    [    0.000000] PERCPU: Embedded 8 pages/cpu @dfa49000 s8640 r8192 d15936 u32768
    [    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 128768
    [    0.000000] Kernel command line: console=ttyO2,115200n8 elevator=noop root=PARTUUID=ca07eee5-02 rw rootwait earlyprintk fixrtc omapdrm.num_crtc=2 consoleblank=0 cma=64M rootfstype=ext4 snd.slots_reserved=1,1
    [    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
    [    0.000000] Memory: 272140K/519168K available (6959K kernel code, 910K rwdata, 3792K rodata, 384K init, 266K bss, 247028K reserved, 0K highmem)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    [    0.000000]     vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0xc0008000 - 0xc0a880cc   (10753 kB)
    [    0.000000]       .init : 0xc0a89000 - 0xc0ae91c0   ( 385 kB)
    [    0.000000]       .data : 0xc0aea000 - 0xc0bcd9a0   ( 911 kB)
    [    0.000000]        .bss : 0xc0bcd9ac - 0xc0c104fc   ( 267 kB)
    [    0.000000] Preemptible hierarchical RCU implementation.
    [    0.000000] NR_IRQS:16 nr_irqs:16 16
    [    0.000000] OMAP clockevent source: timer1 at 31475 Hz
    [    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns
    [    0.000030] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000396] Architected cp15 timer(s) running at 5.90MHz (virt).
    [    0.000432] sched_clock: 56 bits at 5MHz, resolution 169ns, wraps every 2911033065472ns
    [    0.000440] Switching to timer-based delay loop
    [    0.001463] Console: colour dummy device 80x30
    [    0.001482] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
    [    0.001488] This ensures that you still see kernel messages. Please
    [    0.001494] update your kernel commandline.
    [    0.001506] Calibrating delay loop (skipped), value calculated using timer frequency.. 11.80 BogoMIPS (lpj=59016)
    [    0.001519] pid_max: default: 32768 minimum: 301
    [    0.001629] Security Framework initialized
    [    0.001681] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.001692] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.026365] CPU: Testing write buffer coherency: ok
    [    0.026625] /cpus/cpu@0 missing clock-frequency property
    [    0.026661] /cpus/cpu@1 missing clock-frequency property
    [    0.026672] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.026699] Setting up static identity map for 0x806d1da8 - 0x806d1e18
    [    0.080819] CPU1: Booted secondary processor
    [    0.080847] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.080973] Brought up 2 CPUs
    [    0.080989] SMP: Total of 2 processors activated (23.60 BogoMIPS).
    [    0.080996] CPU: All CPU(s) started in SVC mode.
    [    0.081417] devtmpfs: initialized
    [    0.082158] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.083874] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.097180] omap_hwmod: tptc0 using broken dt data from edma-controller
    [    0.097688] omap_hwmod: tptc1 using broken dt data from edma-controller
    [    0.268503] pinctrl core: initialized pinctrl subsystem
    [    0.269250] regulator-dummy: no parameters
    [    0.273662] NET: Registered protocol family 16
    [    0.275538] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.277617] cpuidle: using governor ladder
    [    0.277627] cpuidle: using governor menu
    [    0.324610] syscon 4a002000.tisysconcore: regmap [mem 0x4a002000-0x4a0026cf] registered
    [    0.324944] syscon 4a002e00.tisyscon: regmap [mem 0x4a002e00-0x4a002e7b] registered
    [    0.327771] OMAP GPIO hardware version 0.1
    [    0.334110] irq: no irq domain found for /ocp/pinmux@4a003400 !
    [    0.341558] platform 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000
    [    0.341864] platform 55020000.ipu: assigned reserved memory node ipu2_cma@95800000
    [    0.342159] platform 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
    [    0.357767] platform 41000000.dsp: assigned reserved memory node dsp2_cma@9f000000
    [    0.362310] No ATAGs?
    [    0.362338] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
    [    0.362347] hw-breakpoint: maximum watchpoint size is 8 bytes.
    [    0.365262] OMAP DMA hardware revision 0.0
    [    0.393533] bio: create slab <bio-0> at 0
    [    0.408552] edma-dma-engine edma-dma-engine.0: TI EDMA DMA engine driver
    [    0.416240] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver
    [    0.417067] evm_3v3_sd: 3300 mV
    [    0.417388] evm_3v3_sw: 3300 mV
    [    0.417456] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to find supply vin
    [    0.417644] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to register regulator: -517
    [    0.417664] platform fixedregulator-evm_3v3_sw: Driver reg-fixed-voltage requests probe deferral
    [    0.417914] aic_dvdd: 1800 mV
    [    0.417975] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to find supply vin
    [    0.418151] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to register regulator: -517
    [    0.418170] platform fixedregulator-aic_dvdd: Driver reg-fixed-voltage requests probe deferral
    [    0.418420] vmmcwl_fixed: 1800 mV
    [    0.418733] vtt_fixed: 1350 mV
    [    0.418778] reg-fixed-voltage fixedregulator-vtt: Failed to find supply vin
    [    0.418954] reg-fixed-voltage fixedregulator-vtt: Failed to register regulator: -517
    [    0.418972] platform fixedregulator-vtt: Driver reg-fixed-voltage requests probe deferral
    [    0.422527] vgaarb: loaded
    [    0.422991] i2c-core: driver [palmas] using legacy suspend method
    [    0.423001] i2c-core: driver [palmas] using legacy resume method
    [    0.423608] SCSI subsystem initialized
    [    0.424898] usbcore: registered new interface driver usbfs
    [    0.425065] usbcore: registered new interface driver hub
    [    0.425250] usbcore: registered new device driver usb
    [    0.427582] palmas 0-0058: IRQ missing: skipping irq request
    [    0.427950] palmas 0-0058: Muxing GPIO a, PWM 0, LED 0
    [    0.428100] prom_parse: Bad cell count for /ocp/i2c@48070000/tps659038@58
    [    0.430276] smps12: 850 <--> 1250 mV at 1010 mV
    [    0.431823] smps3: 850 <--> 1250 mV at 1350 mV
    [    0.433510] smps45: 850 <--> 1150 mV at 970 mV
    [    0.435176] smps6: 850 <--> 1250 mV at 1050 mV
    [    0.436682] smps7: 850 <--> 1060 mV at 970 mV
    [    0.438349] smps8: 850 <--> 1250 mV at 980 mV
    [    0.439850] smps9: 1800 mV
    [    0.442287] ldo1: 1800 <--> 3300 mV at 3000 mV
    [    0.451102] ldo2: 3300 mV
    [    0.461281] ldo3: 1800 mV
    [    0.462180] LDO4: no parameters
    [    0.462769] LDO5: no parameters
    [    0.463389] LDO6: no parameters
    [    0.463978] LDO7: no parameters
    [    0.464587] LDO8: no parameters
    [    0.471129] ldo9: 1050 mV
    [    0.481152] ldoln: 1800 mV
    [    0.491220] ldousb: 3300 mV
    [    0.492128] regen1: no parameters
    [    0.492712] regen2: no parameters
    [    0.493414] sysen1: no parameters
    [    0.494009] sysen2: no parameters
    [    0.494280] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
    [    0.495173] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
    [    0.495240] omap_i2c 4807a000.i2c: could not find pctldev for node /ocp/padconf@4844a000/pinmux_i2c4_pins, deferring probe
    [    0.495256] platform 4807a000.i2c: Driver omap_i2c requests probe deferral
    [    0.495670] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
    [    0.495960] media: Linux media interface: v0.10
    [    0.496108] Linux video capture interface: v2.00
    [    0.496329] pps_core: LinuxPPS API ver. 1 registered
    [    0.496338] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [    0.496451] PTP clock support registered
    [    0.497910] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
    [    0.498358] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
    [    0.499404] omap-iommu 40d01000.mmu: 40d01000.mmu registered
    [    0.499510] omap-iommu 40d02000.mmu: 40d02000.mmu registered
    [    0.499612] omap-iommu 58882000.mmu: 58882000.mmu registered
    [    0.499719] omap-iommu 55082000.mmu: 55082000.mmu registered
    [    0.499894] omap-iommu 41501000.mmu: 41501000.mmu registered
    [    0.500002] omap-iommu 41502000.mmu: 41502000.mmu registered
    [    0.500771] Advanced Linux Sound Architecture Driver Initialized.
    [    0.502179] Switched to clocksource arch_sys_counter
    [    0.520578] NET: Registered protocol family 2
    [    0.521269] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
    [    0.521309] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
    [    0.521379] TCP: Hash tables configured (established 4096 bind 4096)
    [    0.521415] TCP: reno registered
    [    0.521428] UDP hash table entries: 256 (order: 1, 8192 bytes)
    [    0.521448] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
    [    0.521633] NET: Registered protocol family 1
    [    0.521892] RPC: Registered named UNIX socket transport module.
    [    0.521901] RPC: Registered udp transport module.
    [    0.521908] RPC: Registered tcp transport module.
    [    0.521915] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [    0.523071] hw perfevents: enabled with ARMv7 Cortex-A15 PMU driver, 7 counters available
    [    0.526010] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.644241] VFS: Disk quotas dquot_6.5.2
    [    0.644349] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
    [    0.644949] NFS: Registering the id_resolver key type
    [    0.644985] Key type id_resolver registered
    [    0.644994] Key type id_legacy registered
    [    0.645027] jffs2: version 2.2. (NAND) (SUMMARY)  c 2001-2006 Red Hat, Inc.
    [    0.645214] msgmni has been set to 979
    [    0.649194] alg: No test for stdrng (krng)
    [    0.649376] NET: Registered protocol family 38
    [    0.649404] io scheduler noop registered (default)
    [    0.649413] io scheduler deadline registered
    [    0.649447] io scheduler cfq registered
    [    0.655672] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
    [    0.694606] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
    [    0.694621] pci_bus 0000:00: root bus resource [io  0x1000-0x10000]
    [    0.694632] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
    [    0.694644] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
    [    0.695168] PCI: bus0: Fast back to back transfers disabled
    [    0.695407] PCI: bus1: Fast back to back transfers enabled
    [    0.695525] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
    [    0.695541] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
    [    0.695555] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.695576] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.699433] pbias_mmc_omap5: 1800 <--> 3000 mV at 3000 mV
    [    0.700213] abb_mpu: 1100 <--> 1210 mV
    [    0.700577] abb_ivahd: 1060 <--> 1250 mV
    [    0.700927] abb_dspeve: 1060 <--> 1250 mV
    [    0.701281] abb_gpu: 1060 <--> 1280 mV
    [    0.702461] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
    [    0.706905] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 299, base_baud = 3000000) is a 8250
    [    0.707675] 4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 300, base_baud = 3000000) is a 8250
    [    0.708440] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 301, base_baud = 3000000) is a 8250
    [    1.857937] console [ttyS2] enabled
    [    1.862344] 48066000.serial: ttyS4 at MMIO 0x48066000 (irq = 302, base_baud = 3000000) is a 8250
    [    1.871954] 48420000.serial: ttyS6 at MMIO 0x48420000 (irq = 303, base_baud = 3000000) is a 8250
    [    1.882568] omap_rng 48090000.rng: OMAP Random Number Generator ver. 20
    [    1.889721] [drm] Initialized drm 1.1.0 20060810
    [    1.904931] brd: module loaded
    [    1.913488] loop: module loaded
    [    1.916975] (hci_tty): inside hci_tty_init
    [    1.921434] (hci_tty): allocated 249, 0
    [    1.927728] ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
    [    1.934495] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
    [    1.943076] ahci 4a140000.sata: flags: 64bit ncq sntf stag pm led clo only pmp pio slum part ccc apst
    [    1.953560] scsi0 : ahci_platform
    [    1.957366] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 336
    [    1.966655] mtdoops: mtd device (mtddev=name/number) must be supplied
    [    1.978486] usbcore: registered new interface driver asix
    [    1.984075] usbcore: registered new interface driver ax88179_178a
    [    1.990335] usbcore: registered new interface driver cdc_ether
    [    1.996368] usbcore: registered new interface driver smsc95xx
    [    2.002292] usbcore: registered new interface driver net1080
    [    2.008114] usbcore: registered new interface driver cdc_subset
    [    2.014219] usbcore: registered new interface driver zaurus
    [    2.019995] usbcore: registered new interface driver cdc_ncm
    [    2.026113] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    [    2.032684] ehci-pci: EHCI PCI platform driver
    [    2.037288] ehci-omap: OMAP-EHCI Host Controller driver
    [    2.043086] usbcore: registered new interface driver cdc_wdm
    [    2.048929] usbcore: registered new interface driver usb-storage
    [    2.056083] mousedev: PS/2 mouse device common for all mice
    [    2.063844] i2c-core: driver [rtc-ds1307] using legacy suspend method
    [    2.070312] i2c-core: driver [rtc-ds1307] using legacy resume method
    [    2.077388] omap_rtc 48838000.rtcss: rtc core: registered 48838000.rtcss as rtc0
    [    2.085710] i2c /dev entries driver
    [    2.312210] ata1: SATA link down (SStatus 0 SControl 300)
    [    3.082232] omap_i2c 48072000.i2c: controller timed out
    [    3.102208] tvp5158 1-0058: i2c i/o error: rc == -110 (should be 1)
    [    4.102205] omap_i2c 48072000.i2c: controller timed out
    [    4.122206] tvp5158 1-0058: i2c i/o error: rc == -110 (should be 1)
    [    4.128501] tvp5158 1-0058: ERROR: Chip id is not TVP5158
    [    4.134867] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
    [    4.141003] vip 48970000.vip: No explicit pinctrl resources data.
    [    4.148120] vip 48970000.vip: loading firmware vpdma-1b8.bin
    [    4.154101] vpe 489d0000.vpe: Device registered as /dev/video0
    [    4.160124] Driver for 1-wire Dallas network protocol.
    [    4.166386] coproc iva_coproc: probe
    [    4.170092] Adding alias for supply vdd,iva_coproc -> vdd,4a0025cc.voltdm
    [    4.176940] vip 48970000.vip: VPDMA firmware loaded
    [    4.181933] vip1-s1: Port A enabled but no endpoints found
    [    4.187289] Adding alias for supply vbb,iva_coproc -> vbb,4a0025cc.voltdm
    [    4.194310] vip1-s0: Port B enabled but no endpoints found
    [    4.199647] vip1-s1: Port B enabled but no endpoints found[    4.206593] coproc iva_coproc: coproc_probe result=0
    [    4.211620] coproc dsp_coproc: probe
    [    4.215307] Adding alias for supply vdd,dsp_coproc -> vdd,4a0025e0.voltdm
    [    4.222125] Adding alias for supply vbb,dsp_coproc -> vbb,4a0025e0.voltdm
    [    4.230382] coproc dsp_coproc: coproc_probe result=0
    [    4.239629] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
    [    4.283306] ledtrig-cpu: registered to indicate activity on CPUs
    [    4.289651] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
    [    4.311810] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
    [    4.318136] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
    [    4.324532] alg: skcipher: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.332208] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.340332] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.353349] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
    [    4.359141] mmc0: host does not support reading read-only switch. assuming write-enable.
    [    4.369261] mmc0: new high speed SDHC card at address 1234
    [    4.375438] mmcblk0: mmc0:1234 SA04G 3.70 GiB
    [    4.382054]  mmcblk0: p1 p2
    [    4.402995] usbcore: registered new interface driver usbhid
    [    4.408592] usbhid: USB HID core driver
    [    4.413578]  remoteproc0: 58820000.ipu is available
    [    4.418479]  remoteproc0: Note: remoteproc is still under development and considered experimental.
    [    4.427534]  remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.438053]  remoteproc0: Direct firmware load failed with error -2
    [    4.444467]  remoteproc1: 55020000.ipu is available
    [    4.449365]  remoteproc1: Note: remoteproc is still under development and considered experimental.
    [    4.458381]  remoteproc0: Falling back to user helper
    [    4.463635]  remoteproc1: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.474172]  remoteproc1: Direct firmware load failed with error -2
    [    4.480466]  remoteproc1: Falling back to user helper
    [    4.485667]  remoteproc2: 40800000.dsp is available
    [    4.490565]  remoteproc2: Note: remoteproc is still under development and considered experimental.
    [    4.499878]  remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.510393]  remoteproc2: Direct firmware load failed with error -2
    [    4.516932]  remoteproc3: 41000000.dsp is available
    [    4.521831]  remoteproc3: Note: remoteproc is still under development and considered experimental.
    [    4.530850]  remoteproc2: Falling back to user helper
    [    4.532224]  remoteproc3: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.532342]  remoteproc3: Direct firmware load failed with error -2
    [    4.532345]  remoteproc3: Falling back to user helper
    [    4.580290] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    4.588346] davinci-mcasp 48468000.mcasp: numevt will be ignored due to errata i868
    [    4.596992] ------------[ cut here ]------------
    [    4.597026] davinci-mcasp 4846c000.mcasp: numevt will be ignored due to errata i868
    [    4.609330] WARNING: CPU: 0 PID: 0 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x234/0x354()
    [    4.618677] 44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4_PER2_P3 (Read): Data Access in User mode during Functional access
    [    4.630288] Modules linked in:
    [    4.633364] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.14.49 #65
    [    4.639481] Backtrace:
    [    4.641955] [<c0012110>] (dump_backtrace) from [<c00122ac>] (show_stack+0x18/0x1c)
    [    4.649555]  r6:00000000 r5:ffffffff r4:00000000 r3:00000000
    [    4.655277] [<c0012294>] (show_stack) from [<c06c7f28>] (dump_stack+0x7c/0xc8)
    [    4.662537] [<c06c7eac>] (dump_stack) from [<c004684c>] (warn_slowpath_common+0x70/0x94)
    [    4.670659]  r6:c02d1a80 r5:00000009 r4:c0aebd90 r3:c0aea000
    [    4.676383] [<c00467dc>] (warn_slowpath_common) from [<c0046914>] (warn_slowpath_fmt+0x38/0x40)
    [    4.685116]  r8:c070823c r7:c09c6cc4 r6:c09c6d30 r5:80080003 r4:d0982550
    [    4.691894] [<c00468e0>] (warn_slowpath_fmt) from [<c02d1a80>] (l3_interrupt_handler+0x234/0x354)
    [    4.700801]  r3:d0982840 r2:c09c6df0
    [    4.704413] [<c02d184c>] (l3_interrupt_handler) from [<c0082e50>] (handle_irq_event_percpu+0x54/0x1a0)
    [    4.713757]  r10:d094b680 r9:c0bcd4c1 r8:00000017 r7:00000000 r6:00000000 r5:d094b6dc
    [    4.721659]  r4:d09821c0
    [    4.724215] [<c0082dfc>] (handle_irq_event_percpu) from [<c0082fe0>] (handle_irq_event+0x44/0x64)
    [    4.733121]  r10:00000001 r9:c0bcd4bf r8:00000000 r7:00000017 r6:d09821c0 r5:d094b6dc
    [    4.741021]  r4:d094b680
    [    4.743576] [<c0082f9c>] (handle_irq_event) from [<c0086128>] (handle_fasteoi_irq+0xa0/0x160)
    [    4.752134]  r6:c0aea000 r5:d094b6dc r4:d094b680 r3:00000000
    [    4.757854] [<c0086088>] (handle_fasteoi_irq) from [<c0082768>] (generic_handle_irq+0x28/0x38)
    [    4.766500]  r5:c0ae7f48 r4:00000017
    [    4.770111] [<c0082740>] (generic_handle_irq) from [<c000f46c>] (handle_IRQ+0x54/0xb8)
    [    4.778058]  r4:c0af2c74 r3:000001ab
    [    4.781665] [<c000f418>] (handle_IRQ) from [<c0008660>] (gic_handle_irq+0x30/0x64)
    [    4.789264]  r8:c0bcd4bf r7:fa212000 r6:c0aebf30 r5:c0af2df8 r4:fa21200c r3:000000c0
    [    4.797086] [<c0008630>] (gic_handle_irq) from [<c06cda80>] (__irq_svc+0x40/0x74)
    [    4.804600] Exception stack(0xc0aebf30 to 0xc0aebf78)
    [    4.809671] bf20:                                     ffffffed 1ef62000 c0af36e4 c001f940
    [    4.817884] bf40: c0aea000 00000000 c0af299c c06d81cc c0bcd4bf c0bcd4bf 00000001 c0aebf84
    [    4.826096] bf60: c0aebf78 c0aebf78 c000f838 c000f828 60000113 ffffffff
    [    4.832736]  r7:c0aebf64 r6:ffffffff r5:60000113 r4:c000f828
    [    4.838456] [<c000f7f8>] (arch_cpu_idle) from [<c0082464>] (cpu_startup_entry+0x68/0x158)
    [    4.846672] [<c00823fc>] (cpu_startup_entry) from [<c06c2618>] (rest_init+0x78/0x90)
    [    4.854444]  r7:c0ad0250 r3:c0aea000
    [    4.858057] [<c06c25a0>] (rest_init) from [<c0a89b44>] (start_kernel+0x310/0x374)
    [    4.865568]  r4:c0af2a80 r3:c0aea000
    [    4.869175] [<c0a89834>] (start_kernel) from [<80008074>] (0x80008074)
    [    4.875728]  r8:8000406a r7:c0af7190 r6:c0ad024c r5:c0af292c r4:10c5387d
    [    4.882508] ---[ end trace 82162b8ec001a7b0 ]---
    [    4.888714] oprofile: using timer interrupt.
    [    4.893165] nf_conntrack version 0.5.0 (7836 buckets, 31344 max)
    [    4.899647] ip_tables: (C) 2000-2006 Netfilter Core Team
    [    4.905072] TCP: cubic registered
    [    4.908401] Initializing XFRM netlink socket
    [    4.912717] NET: Registered protocol family 17
    [    4.917195] NET: Registered protocol family 15
    [    4.921720] Bridge firewalling registered
    [    4.925767] can: controller area network core (rev 20120528 abi 9)
    [    4.932037] NET: Registered protocol family 29
    [    4.936516] can: raw protocol (rev 20120528)
    [    4.940842] 8021q: 802.1Q VLAN Support v1.8
    [    4.945092] Key type dns_resolver registered
    [    4.949381] NET: Registered protocol family 41
    [    4.954591] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.voltdm
    [    4.960888] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.voltdm
    [    4.967544] cpu cpu0: of_pm_voltdm_notifier_register: Fail calculating voltage latency[1100000<->1100000]:-22
    [    4.978161] Power Management for TI OMAP4+ devices.
    [    4.983263] ThumbEE CPU extension supported.
    [    4.987562] Registering SWP/SWPB emulation handler
    [    4.992389] SmartReflex Class3 initialized
    [    4.998389] vmmcwl_fixed: disabling
    [    5.001895] regulator-dummy: disabling
    [    5.005955] dmm 4e000000.dmm: workaround for errata i878 in use
    [    5.014201] dmm 4e000000.dmm: initialized all PAT entries
    [    5.021692] evm_3v3_sw: 3300 mV
    [    5.025055] evm_3v3_sw: supplied by sysen1
    [    5.029739] aic_dvdd: 1800 mV
    [    5.032893] aic_dvdd: supplied by evm_3v3_sw
    [    5.037544] vtt_fixed: 1350 mV
    [    5.040732] vtt_fixed: supplied by sysen2
    [    6.042274] omap_i2c 4807a000.i2c: controller timed out
    [    6.062224] pcf857x: probe of 3-0021 failed with error -110
    [    6.068009] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
    [    6.074294] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    6.081937] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    6.132212] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
    [    6.138335] davinci_mdio 48485000.mdio: detected phy mask fffffff8
    [    6.150596] libphy: 48485000.mdio: probed
    [    6.154644] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver unknown
    [    6.162698] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver unknown
    [    6.171301] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    6.179123] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    6.186675] cpsw 48484000.ethernet: Detected MACID = 7c:ec:79:9c:14:5a
    [    6.193795] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    6.201432] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    6.209606] cpsw 48484000.ethernet: cpsw: Detected MACID = 7c:ec:79:9d:69:5d
    [    6.217970] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    6.225744] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    6.233293] omap_rtc 48838000.rtcss: setting system clock to 2000-01-01 00:00:04 UTC (946684804)
    [    6.242117] sr_init: No PMIC hook to init smartreflex
    [    6.247562] sr_init: platform driver register failed for SR
    [    6.266019] ALSA device list:
    [    6.269004]   No soundcards found.
    [    7.169527] EXT4-fs (mmcblk0p2): recovery complete
    [    7.180644] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    [    7.188809] VFS: Mounted root (ext4 filesystem) on device 179:2.
    [    7.197202] devtmpfs: mounted
    [    7.200436] Freeing unused kernel memory: 384K (c0a89000 - c0ae9000)
    [    7.238689] Unhandled fault: imprecise external abort (0x1406) at 0x00000000
    [    7.245957] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
    [    7.245957]
    [    7.255138] CPU0: stopping
    [    7.257862] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W    3.14.49 #65
    [    7.264940] Backtrace:
    [    7.267418] [<c0012110>] (dump_backtrace) from [<c00122ac>] (show_stack+0x18/0x1c)
    [    7.275019]  r6:00000000 r5:ffffffff r4:00000000 r3:00000000
    [    7.280742] [<c0012294>] (show_stack) from [<c06c7f28>] (dump_stack+0x7c/0xc8)
    [    7.287998] [<c06c7eac>] (dump_stack) from [<c0014b74>] (handle_IPI+0x154/0x180)
    [    7.295422]  r6:c0af2c74 r5:00000005 r4:00000000 r3:c0aea000
    [    7.301141] [<c0014a20>] (handle_IPI) from [<c000868c>] (gic_handle_irq+0x5c/0x64)
    [    7.308740]  r10:00000001 r9:c0bcd4bf r8:c0bcd4bf r7:fa212000 r6:c0aebf30 r5:c0af2df8
    [    7.316646]  r4:fa21200c r3:c002d404
    [    7.320258] [<c0008630>] (gic_handle_irq) from [<c06cda80>] (__irq_svc+0x40/0x74)
    [    7.327771] Exception stack(0xc0aebf30 to 0xc0aebf78)
    [    7.332843] bf20:                                     ffffffed 1ef62000 c0af36e4 c002f178
    [    7.341056] bf40: c0aea000 00000000 c0af299c c06d81cc c0bcd4bf c0bcd4bf 00000001 c0aebf84
    [    7.349267] bf60: c0aebf78 c0aebf78 c002d404 c000f828 a0000113 ffffffff
    [    7.355906]  r7:c0aebf64 r6:ffffffff r5:a0000113 r4:c000f828
    [    7.361630] [<c000f7f8>] (arch_cpu_idle) from [<c0082464>] (cpu_startup_entry+0x68/0x158)
    [    7.369847] [<c00823fc>] (cpu_startup_entry) from [<c06c2618>] (rest_init+0x78/0x90)
    [    7.377619]  r7:c0ad0250 r3:c0aea000
    [    7.381230] [<c06c25a0>] (rest_init) from [<c0a89b44>] (start_kernel+0x310/0x374)
    [    7.388742]  r4:c0af2a80 r3:c0aea000
    [    7.392348] [<c0a89834>] (start_kernel) from [<80008074>] (0x80008074)
    
    

    2017_08_03_CB_mcasp4_kernel_panic_2.txt
    U-Boot SPL 2014.07 (Aug 02 2017 - 18:05:53)
    DRA752-GP ES1.1
    before do_io_settings
    before prcm_init
            |-before enable_basic_clocks
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
    Enable clock module - 4a008728
    Enable clock module - 4a008b30
    Enable clock module - 4a008b38
    Enable clock module - 4a008d20
    Enable clock module - 4ae07838
    Enable clock module - 4a009760
    Enable clock module - 4a009768
    Enable clock module - 4a009770
    Enable clock module - 4a009778
    Enable clock module - 4a009780
    Enable clock module - 4a009810
    Enable clock module - 4a009818
    Enable clock module - 4a008778
    Enable clock module - 4a008780
    Enable clock module - 4ae07840
    Enable clock module - 4a009328
    Enable clock module - 4a009330
    Enable clock module - 4a009738
    Enable clock module - 4ae07830
    Enable clock module - 4a009850
    Enable clock module - 4a0097a0
    Enable clock module - 4a0093d0
    Enable clock module - 4a009838
    Enable clock domain - 4a009700
    Enable clock domain - 4a009300
    Enable clock domain - 4a008b00
    Enable clock domain - 4a008d00
    Enable clock domain - 4a0093c0
    Enable clock domain - 4a008700
            |-before timer_init
            |-before scale_vcores
                    |-before vcores->core
    optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1030, using efuse value 970
                    |-before core
    do_scale_vcore: volt - 970 offset_code - 0x35
                    |-before recalibrate_iodelay
    KEEP 6_30(ETH_SEL) input
    switch to NVA_SDIO (6_29 input).....
    switch to HDMI_I2C_SEL (6_12 input).....
    Power off LGA Board....
                            |-before __recalibrate_iodelay
                                    |-before calibrate_iodelay
                                    |-before isolate_io
                                            |- isolate = 1
                                            |-  wait_on_value1CBBBBB�Kwait_on_value2
    IODELAY: IO delay recalibration successfully completed
                    |-before vcores->mpu
    optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=1090, using efuse value 1010
                    |-before mpu
    do_scale_vcore: volt - 1010 offset_code - 0x39
                    |-before abb_setup
                    |-before mm
                    |-before mm
                    |-before gpu
    optimize_vcore_voltage:efuse 0x4a003b10 bits=16 Vnom=1250, using efuse value 1050
                    |-before gpu
    do_scale_vcore: volt - 1050 offset_code - 0x3d
                    |-before eve
    optimize_vcore_voltage:efuse 0x4a0025e0 bits=16 Vnom=1060, using efuse value 965
                    |-before eve
    do_scale_vcore: volt - 965 offset_code - 0x35
                    |-before iva
    optimize_vcore_voltage:efuse 0x4a0025cc bits=16 Vnom=1060, using efuse value 979
                    |-before iva
    do_scale_vcore: volt - 979 offset_code - 0x36
     |-before setup_dplls
    setup_dplls
    
     core Dpll locked, but not for ideal M = 277,N = 4 values, current values are M = 1330,N= 23
     before core[4a005120] Dpll wait_for_lock
    Core DPLL configured
    
     per Dpll locked, but not for ideal M = 20,N = 0 values, current values are M = 1280,N= ��j�I��KW$�Y?MX8140] Dpll wait_for_lock
    PER DPLL locked
    
     mpu Dpll locked, but not for ideal M = 625,N = 11 values, current values are M = 1470,N= 23
     before mpu[4a005160] Dpll wait_for_lock
    MPU DPLL locked
    
     before usb[4a008180] Dpll wait_for_lock
    
     before ddr[4a005210] Dpll wait_for_lock
    
     before gmac[4a0052a8] Dpll wait_for_lock
     |-before setup_warmreset_time
    before board_early_init_f
    before sdram_init
    >>sdram_init()
    in_sdram = 0
    >>do_sdram_init() 4c000000
    <<do_sdram_init() 4c000000
     size_prog = 20000000
    base=80000000 , maxsize=20000000 , cnt=8000000
    i=27
    get_ram_size() successful<<sdram_init()
    spl_mmc_load_image
    reading dra7-evm.dtb
    spl_load_image_fat_os: error reading image dra7-evm.dtb, err - -1
    reading u-boot.img
    reading u-boot.img
    before init_omap_revision
    before hw_data_init
    before watchdog_init
    before set_mux_conf_regs
    before prcm_init
    
    
    U-Boot 2014.07 (Aug 02 2017 - 18:05:53)
    
    CPU  : DRA752-GP ES1.1
    Board: DRA7xx
    I2C:   ready
    DRAM:  >>sdram_init()
    512 MiB
    NAND:  0 MiB
    MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
    *** Error - No Valid Environment Area found
    *** Warning - bad CRC, using default environment
    
    serial# not set, setting...
    SATA link 0 timeout.
    AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
    flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
    scanning bus for devices...
    Found 0 device(s).
    SCSI:  Net:   cpsw
    Hit any key to stop autoboot:  0
    U-Boot#
    U-Boot#
    U-Boot# pwr_on_j6_sd
    Turn on SATA
    SATA SEL
    Turn on ULPI
    Turn on PCIE
    Turn the 6165 and 1512 on.....
    U-Boot# run boot_cb
    ==== This is CB Ver.F =====
    switch to partitions #0, OK
    mmc0 is current device
    SD/MMC found on device 0
    reading uEnv.txt
    221 bytes read in 3 ms (71.3 KiB/s)
    Loaded environment from uEnv.txt
    Importing environment from mmc0 ...
    5487032 bytes read in 283 ms (18.5 MiB/s)
    102055 bytes read in 27 ms (3.6 MiB/s)
    Booting from mmc0 ...
    Kernel image @ 0x82000000 [ 0x000000 - 0x53b9b8 ]
    ## Flattened Device Tree blob at 88000000
       Booting using the fdt blob at 0x88000000
       Loading Device Tree to 8ffe4000, end 8ffffea6 ... OK
    
    Starting kernel ...
    
    
    Starting kernel 4
    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 3.14.49 (root@louis-VirtualBox) (gcc version 4.7.3 20130226 (prerelease) (crosstool-NG linaro-1.13.1-4.7-2013.03-20130313 - Linaro GCC 2013.03) ) #65 SMP PREEMPT Thu Aug 3 14:50:23 CST 2017
    [    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
    [    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
    [    0.000000] Machine model: TI DRA742 Louis 20170801 09:00
    [    0.000000] Reserved memory: created CMA memory pool at 0x95800000, size 56 MiB
    [    0.000000] Reserved memory: initialized node ipu2_cma@95800000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 64 MiB
    [    0.000000] Reserved memory: initialized node dsp1_cma@99000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9d000000, size 32 MiB
    [    0.000000] Reserved memory: initialized node ipu1_cma@9d000000, compatible id shared-dma-pool
    [    0.000000] Reserved memory: created CMA memory pool at 0x9f000000, size 8 MiB
    [    0.000000] Reserved memory: initialized node dsp2_cma@9f000000, compatible id shared-dma-pool
    [    0.000000] cma: CMA: reserved 64 MiB at 91000000
    [    0.000000] Memory policy: Data cache writealloc
    [    0.000000] DRA752 ES1.1
    [    0.000000] PERCPU: Embedded 8 pages/cpu @dfa49000 s8640 r8192 d15936 u32768
    [    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 128768
    [    0.000000] Kernel command line: console=ttyO2,115200n8 elevator=noop root=PARTUUID=ca07eee5-02 rw rootwait earlyprintk fixrtc omapdrm.num_crtc=2 consoleblank=0 cma=64M rootfstype=ext4 snd.slots_reserved=1,1
    [    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
    [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
    [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
    [    0.000000] Memory: 272140K/519168K available (6959K kernel code, 910K rwdata, 3792K rodata, 384K init, 266K bss, 247028K reserved, 0K highmem)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    [    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    [    0.000000]     vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
    [    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
    [    0.000000]       .text : 0xc0008000 - 0xc0a880cc   (10753 kB)
    [    0.000000]       .init : 0xc0a89000 - 0xc0ae91c0   ( 385 kB)
    [    0.000000]       .data : 0xc0aea000 - 0xc0bcd9a0   ( 911 kB)
    [    0.000000]        .bss : 0xc0bcd9ac - 0xc0c104fc   ( 267 kB)
    [    0.000000] Preemptible hierarchical RCU implementation.
    [    0.000000] NR_IRQS:16 nr_irqs:16 16
    [    0.000000] OMAP clockevent source: timer1 at 31475 Hz
    [    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 65536000000000ns
    [    0.000030] OMAP clocksource: 32k_counter at 32768 Hz
    [    0.000396] Architected cp15 timer(s) running at 5.90MHz (virt).
    [    0.000432] sched_clock: 56 bits at 5MHz, resolution 169ns, wraps every 2911033065472ns
    [    0.000440] Switching to timer-based delay loop
    [    0.001460] Console: colour dummy device 80x30
    [    0.001478] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
    [    0.001485] This ensures that you still see kernel messages. Please
    [    0.001491] update your kernel commandline.
    [    0.001504] Calibrating delay loop (skipped), value calculated using timer frequency.. 11.80 BogoMIPS (lpj=59016)
    [    0.001517] pid_max: default: 32768 minimum: 301
    [    0.001626] Security Framework initialized
    [    0.001678] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.001689] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
    [    0.026150] CPU: Testing write buffer coherency: ok
    [    0.026410] /cpus/cpu@0 missing clock-frequency property
    [    0.026446] /cpus/cpu@1 missing clock-frequency property
    [    0.026457] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    [    0.026485] Setting up static identity map for 0x806d1da8 - 0x806d1e18
    [    0.080820] CPU1: Booted secondary processor
    [    0.080848] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    [    0.080972] Brought up 2 CPUs
    [    0.080988] SMP: Total of 2 processors activated (23.60 BogoMIPS).
    [    0.080996] CPU: All CPU(s) started in SVC mode.
    [    0.081413] devtmpfs: initialized
    [    0.082149] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
    [    0.083861] omap_hwmod: l3_main_2 using broken dt data from ocp
    [    0.097176] omap_hwmod: tptc0 using broken dt data from edma-controller
    [    0.097685] omap_hwmod: tptc1 using broken dt data from edma-controller
    [    0.267743] pinctrl core: initialized pinctrl subsystem
    [    0.268492] regulator-dummy: no parameters
    [    0.272872] NET: Registered protocol family 16
    [    0.274747] DMA: preallocated 256 KiB pool for atomic coherent allocations
    [    0.276811] cpuidle: using governor ladder
    [    0.276822] cpuidle: using governor menu
    [    0.323798] syscon 4a002000.tisysconcore: regmap [mem 0x4a002000-0x4a0026cf] registered
    [    0.324128] syscon 4a002e00.tisyscon: regmap [mem 0x4a002e00-0x4a002e7b] registered
    [    0.326934] OMAP GPIO hardware version 0.1
    [    0.333310] irq: no irq domain found for /ocp/pinmux@4a003400 !
    [    0.340787] platform 58820000.ipu: assigned reserved memory node ipu1_cma@9d000000
    [    0.341096] platform 55020000.ipu: assigned reserved memory node ipu2_cma@95800000
    [    0.341395] platform 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
    [    0.357039] platform 41000000.dsp: assigned reserved memory node dsp2_cma@9f000000
    [    0.361596] No ATAGs?
    [    0.361624] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
    [    0.361634] hw-breakpoint: maximum watchpoint size is 8 bytes.
    [    0.364548] OMAP DMA hardware revision 0.0
    [    0.392339] bio: create slab <bio-0> at 0
    [    0.409095] edma-dma-engine edma-dma-engine.0: TI EDMA DMA engine driver
    [    0.415139] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver
    [    0.415943] evm_3v3_sd: 3300 mV
    [    0.416261] evm_3v3_sw: 3300 mV
    [    0.416329] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to find supply vin
    [    0.416513] reg-fixed-voltage fixedregulator-evm_3v3_sw: Failed to register regulator: -517
    [    0.416532] platform fixedregulator-evm_3v3_sw: Driver reg-fixed-voltage requests probe deferral
    [    0.416782] aic_dvdd: 1800 mV
    [    0.416842] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to find supply vin
    [    0.417019] reg-fixed-voltage fixedregulator-aic_dvdd: Failed to register regulator: -517
    [    0.417037] platform fixedregulator-aic_dvdd: Driver reg-fixed-voltage requests probe deferral
    [    0.417285] vmmcwl_fixed: 1800 mV
    [    0.417600] vtt_fixed: 1350 mV
    [    0.417646] reg-fixed-voltage fixedregulator-vtt: Failed to find supply vin
    [    0.417823] reg-fixed-voltage fixedregulator-vtt: Failed to register regulator: -517
    [    0.417841] platform fixedregulator-vtt: Driver reg-fixed-voltage requests probe deferral
    [    0.421423] vgaarb: loaded
    [    0.421870] i2c-core: driver [palmas] using legacy suspend method
    [    0.421879] i2c-core: driver [palmas] using legacy resume method
    [    0.422485] SCSI subsystem initialized
    [    0.423737] usbcore: registered new interface driver usbfs
    [    0.423901] usbcore: registered new interface driver hub
    [    0.424086] usbcore: registered new device driver usb
    [    0.426401] palmas 0-0058: IRQ missing: skipping irq request
    [    0.426773] palmas 0-0058: Muxing GPIO a, PWM 0, LED 0
    [    0.426923] prom_parse: Bad cell count for /ocp/i2c@48070000/tps659038@58
    [    0.429114] smps12: 850 <--> 1250 mV at 1010 mV
    [    0.430627] smps3: 850 <--> 1250 mV at 1350 mV
    [    0.433453] smps45: 850 <--> 1150 mV at 970 mV
    [    0.435146] smps6: 850 <--> 1250 mV at 1050 mV
    [    0.436663] smps7: 850 <--> 1060 mV at 970 mV
    [    0.438344] smps8: 850 <--> 1250 mV at 980 mV
    [    0.439865] smps9: 1800 mV
    [    0.441258] ldo1: 1800 <--> 3300 mV at 3000 mV
    [    0.451484] ldo2: 3300 mV
    [    0.461116] ldo3: 1800 mV
    [    0.462025] LDO4: no parameters
    [    0.462615] LDO5: no parameters
    [    0.463213] LDO6: no parameters
    [    0.463816] LDO7: no parameters
    [    0.464412] LDO8: no parameters
    [    0.471141] ldo9: 1050 mV
    [    0.481237] ldoln: 1800 mV
    [    0.491155] ldousb: 3300 mV
    [    0.492066] regen1: no parameters
    [    0.492652] regen2: no parameters
    [    0.493349] sysen1: no parameters
    [    0.493943] sysen2: no parameters
    [    0.494201] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
    [    0.495100] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
    [    0.495166] omap_i2c 4807a000.i2c: could not find pctldev for node /ocp/padconf@4844a000/pinmux_i2c4_pins, deferring probe
    [    0.495182] platform 4807a000.i2c: Driver omap_i2c requests probe deferral
    [    0.495603] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
    [    0.495886] media: Linux media interface: v0.10
    [    0.496034] Linux video capture interface: v2.00
    [    0.496257] pps_core: LinuxPPS API ver. 1 registered
    [    0.496266] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [    0.496379] PTP clock support registered
    [    0.497838] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
    [    0.498284] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
    [    0.499362] omap-iommu 40d01000.mmu: 40d01000.mmu registered
    [    0.499470] omap-iommu 40d02000.mmu: 40d02000.mmu registered
    [    0.499574] omap-iommu 58882000.mmu: 58882000.mmu registered
    [    0.499682] omap-iommu 55082000.mmu: 55082000.mmu registered
    [    0.499858] omap-iommu 41501000.mmu: 41501000.mmu registered
    [    0.499966] omap-iommu 41502000.mmu: 41502000.mmu registered
    [    0.500727] Advanced Linux Sound Architecture Driver Initialized.
    [    0.502145] Switched to clocksource arch_sys_counter
    [    0.520451] NET: Registered protocol family 2
    [    0.521146] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
    [    0.521185] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
    [    0.521256] TCP: Hash tables configured (established 4096 bind 4096)
    [    0.521292] TCP: reno registered
    [    0.521304] UDP hash table entries: 256 (order: 1, 8192 bytes)
    [    0.521325] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
    [    0.521510] NET: Registered protocol family 1
    [    0.521776] RPC: Registered named UNIX socket transport module.
    [    0.521786] RPC: Registered udp transport module.
    [    0.521793] RPC: Registered tcp transport module.
    [    0.521800] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [    0.522955] hw perfevents: enabled with ARMv7 Cortex-A15 PMU driver, 7 counters available
    [    0.525895] futex hash table entries: 512 (order: 3, 32768 bytes)
    [    0.643810] VFS: Disk quotas dquot_6.5.2
    [    0.643917] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
    [    0.644514] NFS: Registering the id_resolver key type
    [    0.644553] Key type id_resolver registered
    [    0.644562] Key type id_legacy registered
    [    0.644593] jffs2: version 2.2. (NAND) (SUMMARY)  c 2001-2006 Red Hat, Inc.
    [    0.644779] msgmni has been set to 979
    [    0.648772] alg: No test for stdrng (krng)
    [    0.648971] NET: Registered protocol family 38
    [    0.649000] io scheduler noop registered (default)
    [    0.649010] io scheduler deadline registered
    [    0.649044] io scheduler cfq registered
    [    0.655290] pinctrl-single 4a003400.pinmux: 281 pins at pa fc003400 size 1124
    [    0.694035] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
    [    0.694050] pci_bus 0000:00: root bus resource [io  0x1000-0x10000]
    [    0.694062] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
    [    0.694074] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
    [    0.694603] PCI: bus0: Fast back to back transfers disabled
    [    0.694849] PCI: bus1: Fast back to back transfers enabled
    [    0.694965] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
    [    0.694982] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
    [    0.694995] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.695017] pci 0000:00:00.0: PCI bridge to [bus 01]
    [    0.698857] pbias_mmc_omap5: 1800 <--> 3000 mV at 3000 mV
    [    0.699646] abb_mpu: 1100 <--> 1210 mV
    [    0.700007] abb_ivahd: 1060 <--> 1250 mV
    [    0.700355] abb_dspeve: 1060 <--> 1250 mV
    [    0.700712] abb_gpu: 1060 <--> 1280 mV
    [    0.701830] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled
    [    0.706311] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 299, base_baud = 3000000) is a 8250
    [    0.707091] 4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 300, base_baud = 3000000) is a 8250
    [    0.707856] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 301, base_baud = 3000000) is a 8250
    [    1.857302] console [ttyS2] enabled
    [    1.861617] 48066000.serial: ttyS4 at MMIO 0x48066000 (irq = 302, base_baud = 3000000) is a 8250
    [    1.871245] 48420000.serial: ttyS6 at MMIO 0x48420000 (irq = 303, base_baud = 3000000) is a 8250
    [    1.881840] omap_rng 48090000.rng: OMAP Random Number Generator ver. 20
    [    1.889012] [drm] Initialized drm 1.1.0 20060810
    [    1.904202] brd: module loaded
    [    1.912790] loop: module loaded
    [    1.916277] (hci_tty): inside hci_tty_init
    [    1.920732] (hci_tty): allocated 249, 0
    [    1.927037] ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
    [    1.933805] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
    [    1.942385] ahci 4a140000.sata: flags: 64bit ncq sntf stag pm led clo only pmp pio slum part ccc apst
    [    1.953151] scsi0 : ahci_platform
    [    1.956958] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 336
    [    1.966249] mtdoops: mtd device (mtddev=name/number) must be supplied
    [    1.978117] usbcore: registered new interface driver asix
    [    1.983708] usbcore: registered new interface driver ax88179_178a
    [    1.989969] usbcore: registered new interface driver cdc_ether
    [    1.996002] usbcore: registered new interface driver smsc95xx
    [    2.001911] usbcore: registered new interface driver net1080
    [    2.007755] usbcore: registered new interface driver cdc_subset
    [    2.013857] usbcore: registered new interface driver zaurus
    [    2.019631] usbcore: registered new interface driver cdc_ncm
    [    2.025758] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    [    2.032330] ehci-pci: EHCI PCI platform driver
    [    2.036934] ehci-omap: OMAP-EHCI Host Controller driver
    [    2.042744] usbcore: registered new interface driver cdc_wdm
    [    2.048588] usbcore: registered new interface driver usb-storage
    [    2.055724] mousedev: PS/2 mouse device common for all mice
    [    2.063489] i2c-core: driver [rtc-ds1307] using legacy suspend method
    [    2.069958] i2c-core: driver [rtc-ds1307] using legacy resume method
    [    2.077031] omap_rtc 48838000.rtcss: rtc core: registered 48838000.rtcss as rtc0
    [    2.085360] i2c /dev entries driver
    [    2.312177] ata1: SATA link down (SStatus 0 SControl 300)
    [    3.082200] omap_i2c 48072000.i2c: controller timed out
    [    3.102176] tvp5158 1-0058: i2c i/o error: rc == -110 (should be 1)
    [    4.102170] omap_i2c 48072000.i2c: controller timed out
    [    4.122174] tvp5158 1-0058: i2c i/o error: rc == -110 (should be 1)
    [    4.128469] tvp5158 1-0058: ERROR: Chip id is not TVP5158
    [    4.134836] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
    [    4.140970] vip 48970000.vip: No explicit pinctrl resources data.
    [    4.148095] vip 48970000.vip: loading firmware vpdma-1b8.bin
    [    4.154070] vpe 489d0000.vpe: Device registered as /dev/video0
    [    4.160091] Driver for 1-wire Dallas network protocol.
    [    4.166344] coproc iva_coproc: probe
    [    4.170055] Adding alias for supply vdd,iva_coproc -> vdd,4a0025cc.voltdm
    [    4.176903] vip 48970000.vip: VPDMA firmware loaded
    [    4.181896] vip1-s1: Port A enabled but no endpoints found
    [    4.187251] Adding alias for supply vbb,iva_coproc -> vbb,4a0025cc.voltdm
    [    4.194273] vip1-s0: Port B enabled but no endpoints found
    [    4.199610] vip1-s1: Port B enabled but no endpoints found[    4.206560] coproc iva_coproc: coproc_probe result=0
    [    4.211583] coproc dsp_coproc: probe
    [    4.215269] Adding alias for supply vdd,dsp_coproc -> vdd,4a0025e0.voltdm
    [    4.222087] Adding alias for supply vbb,dsp_coproc -> vbb,4a0025e0.voltdm
    [    4.230363] coproc dsp_coproc: coproc_probe result=0
    [    4.239623] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
    [    4.283270] ledtrig-cpu: registered to indicate activity on CPUs
    [    4.289599] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
    [    4.311805] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
    [    4.318125] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
    [    4.324502] alg: skcipher: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.331109] mmc0: host does not support reading read-only switch. assuming write-enable.
    [    4.333058] mmc0: new high speed SDHC card at address 1234
    [    4.333570] mmcblk0: mmc0:1234 SA04G 3.70 GiB
    [    4.350227] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.350939]  mmcblk0: p1 p2
    [    4.361161] alg: skcipher-ddst: setkey failed on test 5 for ecb-des-omap: flags=100
    [    4.374074] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
    [    4.399645] usbcore: registered new interface driver usbhid
    [    4.405333] usbhid: USB HID core driver
    [    4.410259]  remoteproc0: 58820000.ipu is available
    [    4.415202]  remoteproc0: Note: remoteproc is still under development and considered experimental.
    [    4.424246]  remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.434778]  remoteproc0: Direct firmware load failed with error -2
    [    4.441072]  remoteproc0: Falling back to user helper
    [    4.446275]  remoteproc1: 55020000.ipu is available
    [    4.451173]  remoteproc1: Note: remoteproc is still under development and considered experimental.
    [    4.460456]  remoteproc1: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.470978]  remoteproc1: Direct firmware load failed with error -2
    [    4.477387]  remoteproc2: 40800000.dsp is available
    [    4.482317]  remoteproc2: Note: remoteproc is still under development and considered experimental.
    [    4.491313]  remoteproc2: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.501725]  remoteproc1: Falling back to user helper
    [    4.507141]  remoteproc2: Direct firmware load failed with error -2
    [    4.513691]  remoteproc3: 41000000.dsp is available
    [    4.518590]  remoteproc3: Note: remoteproc is still under development and considered experimental.
    [    4.527614]  remoteproc2: Falling back to user helper
    [    4.532178]  remoteproc3: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
    [    4.532286]  remoteproc3: Direct firmware load failed with error -2
    [    4.532289]  remoteproc3: Falling back to user helper
    [    4.577046] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    4.585117] davinci-mcasp 48468000.mcasp: numevt will be ignored due to errata i868
    [    4.593734] ------------[ cut here ]------------
    [    4.598391] WARNING: CPU: 0 PID: 1 at drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x234/0x354()
    [    4.607738] 44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4_PER2_P3 (Read): Data Access in User mode during Functional access
    [    4.619348] Modules linked in:
    [    4.622426] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.49 #65
    [    4.628542] Backtrace:
    [    4.631016] [<c0012110>] (dump_backtrace) from [<c00122ac>] (show_stack+0x18/0x1c)
    [    4.638615]  r6:00000000 r5:ffffffff r4:00000000 r3:00000000
    [    4.644336] [<c0012294>] (show_stack) from [<c06c7f28>] (dump_stack+0x7c/0xc8)
    [    4.651595] [<c06c7eac>] (dump_stack) from [<c004684c>] (warn_slowpath_common+0x70/0x94)
    [    4.659717]  r6:c02d1a80 r5:00000009 r4:d0909b60 r3:d0908000
    [    4.665438] [<c00467dc>] (warn_slowpath_common) from [<c0046914>] (warn_slowpath_fmt+0x38/0x40)
    [    4.674170]  r8:c070823c r7:c09c6cc4 r6:c09c6d30 r5:80080003 r4:d0982550
    [    4.680946] [<c00468e0>] (warn_slowpath_fmt) from [<c02d1a80>] (l3_interrupt_handler+0x234/0x354)
    [    4.689853]  r3:d0982840 r2:c09c6df0
    [    4.693466] [<c02d184c>] (l3_interrupt_handler) from [<c0082e50>] (handle_irq_event_percpu+0x54/0x1a0)
    [    4.702808]  r10:d094b680 r9:c0bcd4c1 r8:00000017 r7:00000000 r6:00000000 r5:d094b6dc
    [    4.710711]  r4:d09821c0
    [    4.713266] [<c0082dfc>] (handle_irq_event_percpu) from [<c0082fe0>] (handle_irq_event+0x44/0x64)
    [    4.722173]  r10:d0a9529c r9:d0908000 r8:00000000 r7:00000017 r6:d09821c0 r5:d094b6dc
    [    4.730076]  r4:d094b680
    [    4.732631] [<c0082f9c>] (handle_irq_event) from [<c0086128>] (handle_fasteoi_irq+0xa0/0x160)
    [    4.741189]  r6:d0908000 r5:d094b6dc r4:d094b680 r3:00000000
    [    4.746908] [<c0086088>] (handle_fasteoi_irq) from [<c0082768>] (generic_handle_irq+0x28/0x38)
    [    4.755553]  r5:c0ae7f48 r4:00000017
    [    4.759162] [<c0082740>] (generic_handle_irq) from [<c000f46c>] (handle_IRQ+0x54/0xb8)
    [    4.767110]  r4:c0af2c74 r3:000001ab
    [    4.770718] [<c000f418>] (handle_IRQ) from [<c0008660>] (gic_handle_irq+0x30/0x64)
    [    4.778316]  r8:d080a980 r7:fa212000 r6:d0909d00 r5:c0af2df8 r4:fa21200c r3:000000c0
    [    4.786137] [<c0008630>] (gic_handle_irq) from [<c06cda80>] (__irq_svc+0x40/0x74)
    [    4.793649] Exception stack(0xd0909d00 to 0xd0909d48)
    [    4.798723] 9d00: 00000000 00000005 00000000 d0ac74d0 d0ac7410 00000005 d0821c00 d0ac7410
    [    4.806935] 9d20: d080a980 d0908000 d0a9529c d0909d64 d0909d68 d0909d48 c05cfca0 c03b9684
    [    4.815145] 9d40: 20000113 ffffffff
    [    4.818644]  r7:d0909d34 r6:ffffffff r5:20000113 r4:c03b9684
    [    4.824368] [<c03b965c>] (__pm_runtime_idle) from [<c05cfca0>] (davinci_mcasp_probe+0x8ac/0xa3c)
    [    4.833188]  r7:d0ac7410 r6:d0821c00 r5:c0bc4794 r4:d0d8ee10
    [    4.838909] [<c05cf3f4>] (davinci_mcasp_probe) from [<c03b0e3c>] (platform_drv_probe+0x20/0x50)
    [    4.847642]  r10:c0ad005c r8:00000000 r7:c0bc4574 r6:00000000 r5:c0bc4574 r4:d0ac7410
    [    4.855551] [<c03b0e1c>] (platform_drv_probe) from [<c03af8fc>] (driver_probe_device+0x110/0x238)
    [    4.864457]  r5:d0ac7410 r4:c0c022d8
    [    4.868066] [<c03af7ec>] (driver_probe_device) from [<c03afab8>] (__driver_attach+0x94/0x98)
    [    4.876536]  r8:c0ac2388 r7:00000000 r6:d0ac7444 r5:c0bc4574 r4:d0ac7410 r3:00000000
    [    4.884356] [<c03afa24>] (__driver_attach) from [<c03adf04>] (bus_for_each_dev+0x5c/0x90)
    [    4.892565]  r6:c03afa24 r5:c0bc4574 r4:00000000 r3:00000000
    [    4.898284] [<c03adea8>] (bus_for_each_dev) from [<c03af3f0>] (driver_attach+0x20/0x28)
    [    4.906318]  r6:c0b696f8 r5:d0e12100 r4:c0bc4574
    [    4.910981] [<c03af3d0>] (driver_attach) from [<c03aeff8>] (bus_add_driver+0xdc/0x1dc)
    [    4.918935] [<c03aef1c>] (bus_add_driver) from [<c03b015c>] (driver_register+0x80/0xfc)
    [    4.926969]  r7:c0a8955c r6:c0bcd9c0 r5:00000006 r4:c0bc4574
    [    4.932688] [<c03b00dc>] (driver_register) from [<c03b0d5c>] (__platform_driver_register+0x50/0x64)
    [    4.941769]  r5:00000006 r4:c0ae5f7c
    [    4.945384] [<c03b0d0c>] (__platform_driver_register) from [<c0ac23a0>] (davinci_mcasp_driver_init+0x18/0x20)
    [    4.955343] [<c0ac2388>] (davinci_mcasp_driver_init) from [<c00089a8>] (do_one_initcall+0xf4/0x154)
    [    4.964431] [<c00088b4>] (do_one_initcall) from [<c0a89cac>] (kernel_init_freeable+0x104/0x1d4)
    [    4.973163]  r10:c0ad005c r9:c0ad0050 r8:000000e9 r7:c0a8955c r6:c0bcd9c0 r5:00000006
    [    4.981064]  r4:c0ae5f7c
    [    4.983618] [<c0a89ba8>] (kernel_init_freeable) from [<c06c2640>] (kernel_init+0x10/0xf4)
    [    4.991827]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c06c2630
    [    4.999728]  r4:00000000
    [    5.002281] [<c06c2630>] (kernel_init) from [<c000ec00>] (ret_from_fork+0x14/0x34)
    [    5.009880]  r4:00000000 r3:d0908000
    [    5.013497] ---[ end trace 78d96c7e54069ded ]---
    [    5.018204] davinci-mcasp 4846c000.mcasp: numevt will be ignored due to errata i868
    [    5.027706] oprofile: using timer interrupt.
    [    5.032063] nf_conntrack version 0.5.0 (7836 buckets, 31344 max)
    [    5.038555] ip_tables: (C) 2000-2006 Netfilter Core Team
    [    5.044014] TCP: cubic registered
    [    5.047343] Initializing XFRM netlink socket
    [    5.051642] NET: Registered protocol family 17
    [    5.056138] NET: Registered protocol family 15
    [    5.060665] Bridge firewalling registered
    [    5.064714] can: controller area network core (rev 20120528 abi 9)
    [    5.070984] NET: Registered protocol family 29
    [    5.075463] can: raw protocol (rev 20120528)
    [    5.079788] 8021q: 802.1Q VLAN Support v1.8
    [    5.084036] Key type dns_resolver registered
    [    5.088324] NET: Registered protocol family 41
    [    5.093533] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.voltdm
    [    5.099829] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.voltdm
    [    5.106502] cpu cpu0: of_pm_voltdm_notifier_register: Fail calculating voltage latency[1100000<->1100000]:-22
    [    5.117156] Power Management for TI OMAP4+ devices.
    [    5.122296] ThumbEE CPU extension supported.
    [    5.126597] Registering SWP/SWPB emulation handler
    [    5.131407] SmartReflex Class3 initialized
    [    5.137491] vmmcwl_fixed: disabling
    [    5.140998] regulator-dummy: disabling
    [    5.145077] dmm 4e000000.dmm: workaround for errata i878 in use
    [    5.153405] dmm 4e000000.dmm: initialized all PAT entries
    [    5.160932] evm_3v3_sw: 3300 mV
    [    5.164247] evm_3v3_sw: supplied by sysen1
    [    5.168931] aic_dvdd: 1800 mV
    [    5.172044] aic_dvdd: supplied by evm_3v3_sw
    [    5.176703] vtt_fixed: 1350 mV
    [    5.179891] vtt_fixed: supplied by sysen2
    [    6.182193] omap_i2c 4807a000.i2c: controller timed out
    [    6.202193] pcf857x: probe of 3-0021 failed with error -110
    [    6.207981] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
    [    6.214251] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    6.221892] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    6.272168] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
    [    6.278290] davinci_mdio 48485000.mdio: detected phy mask fffffff8
    [    6.290642] libphy: 48485000.mdio: probed
    [    6.294691] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver unknown
    [    6.302744] davinci_mdio 48485000.mdio: phy[1]: device 48485000.mdio:01, driver unknown
    [    6.311343] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    6.319583] cpsw 48484000.ethernet: Detected MACID = 7c:ec:79:9c:14:5a
    [    6.322206] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    6.322834] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    6.322876] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    6.349088] cpsw 48484000.ethernet: cpsw: Detected MACID = 7c:ec:79:9d:69:5d
    [    6.357577] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    6.365503] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    6.372739] omap_rtc 48838000.rtcss: setting system clock to 2000-01-01 00:00:04 UTC (946684804)
    [    6.381563] sr_init: No PMIC hook to init smartreflex
    [    6.387013] sr_init: platform driver register failed for SR
    [    6.405568] ALSA device list:
    [    6.408553]   No soundcards found.
    [    6.863257] EXT4-fs (mmcblk0p2): recovery complete
    [    6.868080] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    [    6.876251] VFS: Mounted root (ext4 filesystem) on device 179:2.
    [    6.884442] devtmpfs: mounted
    [    6.887668] Freeing unused kernel memory: 384K (c0a89000 - c0ae9000)
    INIT: version 2.88 booting
    [    7.073411] Unhandled fault: imprecise external abort (0x1406) at 0x00000000
    INIT: Entering runlevel: 5
    sed: /proc/mounts: No such file or directory
    sed: /proc/mounts: No such file or directory
    sed: /proc/mounts: No such file or directory
    Configuring network interfaces... ifup: interface lo already configured
    grep: /proc/cmdline: No such file or directory
    done.
    Starting system message bus: [    7.445258] random: dbus-daemon urandom read with 58 bits of entropy available
    Failed to start message bus: Failed to bind socket "/var/run/dbus/system_bus_socket": No such file or directory
    dbus.
    UIM SYSFS Node Not Found
    Starting telnet daemon.
    Starting tiipclad daemon
    GateMP support enabled on host
    
    Opened log file: lad.txt
    
    numProcessors = 5 id = 0 baseId = 0
    
    Spawned daemon: /usr/bin/lad_dra7xx
    
    .
    Starting rpcbind daemon...rpcbind: cannot create socket for udp6
    rpcbind: cannot create socket for tcp6
    done.
    creating NFS state directory: done
    starting statd: done
    grep: /proc/filesystems: No such file or directory
    NFS daemon support not enabled in kernel
    Starting syslogd/klogd: done
    Starting thttpd.
    [    7.767000] net eth0: initializing cpsw version 1.15 (0)
    [    7.776496] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    7.784303] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    7.855848] net eth0: phy found : id is : 0x1410dd1
    [    7.866731] 8021q: adding VLAN 0 to HW filter on device eth0
    [    7.877508] net eth1: initializing cpsw version 1.15 (0)
    [    7.887153] asoc-simple-card sound@0: ASoC: CPU DAI davinci-mcasp.0 not registered
    [    7.894908] platform sound@0: Driver asoc-simple-card requests probe deferral
    [    7.975968] net eth1: phy found : id is : 0x1410dd1
    [    7.985021] 8021q: adding VLAN 0 to HW filter on device eth1
    [    7.999107] device eth0 entered promiscuous mode
    [    8.007608] device eth1 entered promiscuous mode
    [    8.015349] br0: port 2(eth1) entered forwarding state
    [    8.020522] br0: port 2(eth1) entered forwarding state
    /etc/rc5.d/S97_ethernet_init: line 12: /proc/sys/net/ipv4/ip_forward: No such file or directory
    Enabling thermal zones...
    /etc/rc5.d/S98thermal-zone-init: line 7: /sys/class/thermal/thermal_zone*/mode: No such file or directory
    *** Running User Application ***
    Packet dump deactivate
    Stopping Bootlog daemon: bootlogd.
    
    
    
    2017.06.13 11:00 AM
    
    
    This version is for J6
    
    
    [CB_Server_Client.c, main, 842] uart_OpenComport configuration: cport_nr (0), bdrate (115200), mode (8), mode (N), mode (1), mode ()
    [uart.c, uart_OpenComport, 151] uart_OpenComport configuration: Cport[comport_number] (-1)
    unable to open comport : No such file or directory
    [CB_Server_Client.c, main, 845] ______ERROR______ CB can not open com comport
    sh: /sys/class/gpio/gpio146/direction: No such file or directory
    sh: /sys/class/gpio/gpio80/direction: No such file or directory
    sh: /sys/class/gpio/gpio80/value: No such file or directory
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    [    8.872251] br0: port 2(eth1) entered disabled state
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    [   11.858291] libphy: 48485000.mdio:01 - Link is Up - 1000/Full
    [   11.864284] br0: port 1(eth0) entered forwarding state
    [   11.869461] br0: port 1(eth0) entered forwarding state
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    [   21.885598] random: nonblocking pool is initialized
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    [   26.882151] br0: port 1(eth0) entered forwarding state
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    
    
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    
    
    
    
    
    
    cat: can't open '/sys/class/gpio/gpio146/value': No such file or directory
    [CB_Server_Client.c, sync_AB_status, 421] ______ CB GPIO 146 status:  ______
    [CB_Server_Client.c, sync_AB_status, 430] ______ CB GPIO 146 LOW, AB booting ______
    
    

    BRs

    Louis

  • The crash in kernel-3.14 can be caused by missing McASP4's device-tree and hwmod data. Please refer to: arch/arm/mach-omap2/omap_hwmod_7xx_data.c and arch/arm/boot/dts/dra7.dtsi.

    The hwmod data populated in that file only includes the McASP instances that are actually used in the TI EVM. You need to add the hwmod data for the other instances you are using, like McASP4. Similarly, the McASP4 device-tree node in the base dra7.dtsi file needs to be added.

    McASP4 is more similar to McASP6 and McASP7 instances, in terms of having the CFG and DAT ports connected to the same bus. McASP1-3 differ on that regard to the other instances. So, you can use McASP6 as a reference.

    It's worth noting that the kernel-4.4 doesn't have this problem because all McASP instances are populated in the hwmod file as well as in the base dra7.dtsi file.
  • Hi Misael,

    1. MCASP3 & MCASP4 both can work well.

    2. Actually, we still have MCASP1 and MCASP2 need to activate.
    But I cannot find DRA7XX_CM_L4PER2_MCASP1_CLKCTRL_OFFSET and DRA7XX_RM_L4PER2_MCASP1_CONTEXT_OFFSET in file "arch/arm/mach-omap2/cm2_7xx.h" when I try to activate mcasp1 interface.

    Could you please help this issue.
    Thank you very much.

    BRs
    Louis
  • McASP1-3 instances different to the other instances because they are connected to different buses, their DAT port is connected to L3 instead of L4. McASP1 even differs more from the other instances because it's in a different clock domain, it's in IPU1, not in L4PER2. Look for *_IPU1_MCASP1_* offset definitions instead.

    Different topics have been discussed in this e2e post, so I'm going to mark my previous reply as a solution to the original issue because the McASP1 question is a completely different problem. Please create another post if you still have any other questions/issues with McASP.