Am335x: Ethernet connection on GMII2 - board setup (U-Boot)

any luck in making it work?? i wrote my code the same way and have to test it !

Hi Vidin,

thanks, you're right and so it is wired on the board. I fixed this to:

static struct module_pin_mux gmii2_pin_mux[] = {
    {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE},            /* GMII2_RXERR */
    {OFFSET(gpmc_a0), MODE(1)},                /* GMII2_TXEN */
    {OFFSET(gpmc_a1), MODE(1) | RXACTIVE},            /* GMII2_RXDV */
    {OFFSET(gpmc_a2), MODE(1)},                /* GMII2_TXD3 */
    {OFFSET(gpmc_a3), MODE(1)},                /* GMII2_TXD2 */
    {OFFSET(gpmc_a4), MODE(1)},                /* GMII2_TXD1 */
    {OFFSET(gpmc_a5), MODE(1)},                /* GMII2_TXD0 */
    {OFFSET(gpmc_a6), MODE(1) | RXACTIVE},            /* GMII2_TXCLK */
    {OFFSET(gpmc_a7), MODE(1) | RXACTIVE},            /* GMII2_RXCLK */
    {OFFSET(gpmc_a8), MODE(1) | RXACTIVE},            /* GMII2_RXD3 */
    {OFFSET(gpmc_a9), MODE(1) | RXACTIVE},            /* GMII2_RXD2 */
    {OFFSET(gpmc_a10), MODE(1) | RXACTIVE},            /* GMII2_RXD1 */
    {OFFSET(gpmc_a11), MODE(1) | RXACTIVE},            /* GMII2_RXD0 */
    {OFFSET(gpmc_wait0), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_CRS */
    {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_COL */
    {-1},
};
But unfortunately the result stays as already described "wait_for_user_access Timeout".

Thanks and Regards

Arndt

Hi,

What source for U-Boot do you use? Is it TI SDK (which version) or other source?

BR,

Vidin

I'm using upstream U-Boot 2013.07 within an upstream buildroot 2013.08 environment.

Regards

Arndt

Biser,

thanks. I really forgot to configure the MDIO interface. After configuring MDC and MDIO the "wait_for_user_access Timeout" output has stopped. Yes, at MDIO_DATA I have an external pullup resistor.

U-Boot now complains, that the PHY isn't found:

Net:   <ethaddr> not set. Validating first E-fuse MAC
Phy not found
PHY reset timed out
cpsw, usb_ether

Pin setup is now:

static struct module_pin_mux gmii2_pin_mux[] = {
    {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},    /* MDIO_DATA */
    {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
    {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE},            /* GMII2_RXERR */
    {OFFSET(gpmc_a0), MODE(1)},                /* GMII2_TXEN */
    {OFFSET(gpmc_a1), MODE(1) | RXACTIVE},            /* GMII2_RXDV */
    {OFFSET(gpmc_a2), MODE(1)},                /* GMII2_TXD3 */
    {OFFSET(gpmc_a3), MODE(1)},                /* GMII2_TXD2 */
    {OFFSET(gpmc_a4), MODE(1)},                /* GMII2_TXD1 */
    {OFFSET(gpmc_a5), MODE(1)},                /* GMII2_TXD0 */
    {OFFSET(gpmc_a6), MODE(1) | RXACTIVE},            /* GMII2_TXCLK */
    {OFFSET(gpmc_a7), MODE(1) | RXACTIVE},            /* GMII2_RXCLK */
    {OFFSET(gpmc_a8), MODE(1) | RXACTIVE},            /* GMII2_RXD3 */
    {OFFSET(gpmc_a9), MODE(1) | RXACTIVE},            /* GMII2_RXD2 */
    {OFFSET(gpmc_a10), MODE(1) | RXACTIVE},            /* GMII2_RXD1 */
    {OFFSET(gpmc_a11), MODE(1) | RXACTIVE},            /* GMII2_RXD0 */
    {OFFSET(gpmc_wait0), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_CRS */
    {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_COL */
    {-1},
};

Thanks and regards

Arndt

Hi Biser, so I did, but this didn't change anything (for the moment).

Hi Arndt,

Did you try to use the TI U-boot from latest SDK v06.00? It has support especially for AM335x processors.

You can find the LINUXEZSDK-AM335X here: http://www.ti.com/tool/linuxezsdk-sitara

And here it is the release note for it:

http://processors.wiki.ti.com/index.php/Sitara_SDK_6.00.00_Release_Notes

Best regards,

Vidin

Vidin,

because I use a different pinmux and my board doesn't have a programmable PMIC and neither EEPROM nor NAND I have to compile this from sources with my board config. Just to compile for an unmodified am335x_evm board I had to patch drivers/net/cpsw.c, drivers/mtd/nand/omap_gpmc.c and arch/arm/cpu/armv7/omap-common/timer.c to include asm/arch/cpu.h.

In the end I was able to compile an u-boot.img from your recommended SDK-sources, but the result is nearly the same as with my former used upstream sources:

...

Net:   <ethaddr> not set. Validating first E-fuse MAC
PHY reset timed out
...

Best Regards

Arndt

Hi Biser and Vidin,

finally the PHY seems to be detected now. After adjusting CONFIG_PHY_ADDR to 1 (which is the devices default address) I don't get further error messages and link and activity LED are working. In my first try I didn't get an address via DHCP, but for today the improvement is not too bad.

Thanks for your supportiveness.

Kind Regards

Arndt

Hi !

I have the gmii2 pin mux configured as 

static struct module_pin_mux gmii2_pin_mux[] = {
{OFFSET(gpmc_a0), MODE(1)}, /* GMII2_TXEN */
{OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* GMII2_RXDV */
{OFFSET(gpmc_a2), MODE(1)}, /* GMII2_TXD3 */
{OFFSET(gpmc_a3), MODE(1)}, /* GMII2_TXD2 */
{OFFSET(gpmc_a4), MODE(1)}, /* GMII2_TXD1 */
{OFFSET(gpmc_a5), MODE(1)}, /* GMII2_TXD0 */
{OFFSET(gpmc_a6), MODE(1)| RXACTIVE}, /* GMII2_TXCLK */
{OFFSET(gpmc_a7), MODE(1) | RXACTIVE| PULLUP_EN}, /* GMII2_RXCLK */
{OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* GMII2_RXD3 */
{OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* GMII2_RXD2 */
{OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* GMII2_RXD1 */
{OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* GMII2_RXD0 */
{OFFSET(gpmc_wait0), MODE(1) | RXACTIVE }, /* GMII2_crs verify with john*/
{OFFSET(gpmc_wpn), MODE(1) | RXACTIVE}, /* GMII2_rxer*/
{OFFSET(gpmc_be1n), MODE(1) | RXACTIVE| PULLUP_EN},/* GMMI2_COL verify with john*/
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA*/
{OFFSET(mdio_clk), MODE(0)| RXACTIVE| PULLUP_EN}, /* MDIO_MDC */
{-1},

};

My phy is getting detected but i could not able to ping any ip.. My phy is MICREL 8081. I have included the 

#define CONFIG_PHY_MICREL and #define CONFIG_PHY_ADDR 1.  I have verified from the WIreshark that no packets from the Board are sent to the host device.

I am using the same cpsw data

static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 1,
},
};

static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};

i was wondering if any one can has a working gmmi2 setting, please let me know what is the mistake i am doing??

Thanks,

harsha

Hi Biser,

We have verified the mac control register and is set to 1. But still the packets are not coming out of the processor. The CPSW stats are all 0.

These are the settings we are using for GMMi2

static struct cpsw_slave_data cpsw_slaves[] = {

{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 1,
},
};

static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};

Thanks,

harsha