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Am335x: Ethernet connection on GMII2 - board setup (U-Boot)

Arndt Kritzner
Intellectual 720 points
Other Parts Discussed in Thread: DP83848I

Hi,

on a custom Am335x-board I have my ethernet 10/100 PHY (DP83848I) connected as follows to then GMII2-interface:

static struct module_pin_mux gmii2_pin_mux[] = {
    {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE},            /* GMII2_RXERR */
    {OFFSET(gpmc_ad0), MODE(1)},                /* GMII2_TXEN */
    {OFFSET(gpmc_ad1), MODE(1) | RXACTIVE},            /* GMII2_RXDV */
    {OFFSET(gpmc_ad2), MODE(1)},                /* GMII2_TXD3 */
    {OFFSET(gpmc_ad3), MODE(1)},                /* GMII2_TXD2 */
    {OFFSET(gpmc_ad4), MODE(1)},                /* GMII2_TXD1 */
    {OFFSET(gpmc_ad5), MODE(1)},                /* GMII2_TXD0 */
    {OFFSET(gpmc_ad6), MODE(1) | RXACTIVE},            /* GMII2_TXCLK */
    {OFFSET(gpmc_ad7), MODE(1) | RXACTIVE},            /* GMII2_RXCLK */
    {OFFSET(gpmc_ad8), MODE(1) | RXACTIVE},            /* GMII2_RXD3 */
    {OFFSET(gpmc_ad9), MODE(1) | RXACTIVE},            /* GMII2_RXD2 */
    {OFFSET(gpmc_ad10), MODE(1) | RXACTIVE},        /* GMII2_RXD1 */
    {OFFSET(gpmc_ad11), MODE(1) | RXACTIVE},        /* GMII2_RXD0 */
    {OFFSET(gpmc_wait0), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_CRS */
    {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_COL */
    {-1},
};
In my from am335xevm derived board setup for U-Boot (2013.07, upstream) I use unmodified content of cpsw_slaves and cpsw_data (board.c) and initialize with:
    writel(MII_MODE_ENABLE, &cdev->miisel);
    cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
            PHY_INTERFACE_MODE_MII;
But this way the PHY is not detected and U-Boot produces a lot of "wait_for_user_access Timeout"-messages before giving up and coming to the prompt. What am I missing?

Thanks and Regards

Arndt


  • 0
    Intellectual 545 points

    any luck in making it work?? i wrote my code the same way and have to test it !

  • 0
    TI__Intellectual 1340 points

    Hi Arndt,

    As I can see your connection of pins gpmc_ad0 to gpmc_ad11 is wrong. These pins does not have GMII2 functionality on MODE(1).

    The correct pins are gpms_a0 to gpmc_a11 with GMII2 functions on MODE(1).

    Hope this helps,

    BR,

    Vidin

  • 0 in reply to Vidin Tsonev-XID
    Intellectual 720 points

    Hi Vidin,

    thanks, you're right and so it is wired on the board. I fixed this to:

    static struct module_pin_mux gmii2_pin_mux[] = {
        {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE},            /* GMII2_RXERR */
        {OFFSET(gpmc_a0), MODE(1)},                /* GMII2_TXEN */
        {OFFSET(gpmc_a1), MODE(1) | RXACTIVE},            /* GMII2_RXDV */
        {OFFSET(gpmc_a2), MODE(1)},                /* GMII2_TXD3 */
        {OFFSET(gpmc_a3), MODE(1)},                /* GMII2_TXD2 */
        {OFFSET(gpmc_a4), MODE(1)},                /* GMII2_TXD1 */
        {OFFSET(gpmc_a5), MODE(1)},                /* GMII2_TXD0 */
        {OFFSET(gpmc_a6), MODE(1) | RXACTIVE},            /* GMII2_TXCLK */
        {OFFSET(gpmc_a7), MODE(1) | RXACTIVE},            /* GMII2_RXCLK */
        {OFFSET(gpmc_a8), MODE(1) | RXACTIVE},            /* GMII2_RXD3 */
        {OFFSET(gpmc_a9), MODE(1) | RXACTIVE},            /* GMII2_RXD2 */
        {OFFSET(gpmc_a10), MODE(1) | RXACTIVE},            /* GMII2_RXD1 */
        {OFFSET(gpmc_a11), MODE(1) | RXACTIVE},            /* GMII2_RXD0 */
        {OFFSET(gpmc_wait0), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_CRS */
        {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_COL */
        {-1},
    };
    But unfortunately the result stays as already described "wait_for_user_access Timeout".

    Thanks and Regards

    Arndt

  • 0 in reply to Arndt Kritzner
    TI__Intellectual 1340 points

    Hi,

    What source for U-Boot do you use? Is it TI SDK (which version) or other source?

    BR,

    Vidin

  • 0 in reply to Vidin Tsonev-XID
    TI__Guru**** 393215 points
    Arndt,
     
    What about the MDIO interface? The PHY should be detected/configured over it. Do you have RX enabled on MDIO_CLK and MDIO_DATA? Do you have an external pullup resistor on MDIO_DATA?
  • 0 in reply to Vidin Tsonev-XID
    Intellectual 720 points

    I'm using upstream U-Boot 2013.07 within an upstream buildroot 2013.08 environment.

    Regards

    Arndt

  • 0 in reply to Biser Gatchev-XID
    Intellectual 720 points

    Biser,

    thanks. I really forgot to configure the MDIO interface. After configuring MDC and MDIO the "wait_for_user_access Timeout" output has stopped. Yes, at MDIO_DATA I have an external pullup resistor.

    U-Boot now complains, that the PHY isn't found:

    Net:   <ethaddr> not set. Validating first E-fuse MAC
    Phy not found
    PHY reset timed out
    cpsw, usb_ether

    Pin setup is now:

    static struct module_pin_mux gmii2_pin_mux[] = {
        {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},    /* MDIO_DATA */
        {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
        {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE},            /* GMII2_RXERR */
        {OFFSET(gpmc_a0), MODE(1)},                /* GMII2_TXEN */
        {OFFSET(gpmc_a1), MODE(1) | RXACTIVE},            /* GMII2_RXDV */
        {OFFSET(gpmc_a2), MODE(1)},                /* GMII2_TXD3 */
        {OFFSET(gpmc_a3), MODE(1)},                /* GMII2_TXD2 */
        {OFFSET(gpmc_a4), MODE(1)},                /* GMII2_TXD1 */
        {OFFSET(gpmc_a5), MODE(1)},                /* GMII2_TXD0 */
        {OFFSET(gpmc_a6), MODE(1) | RXACTIVE},            /* GMII2_TXCLK */
        {OFFSET(gpmc_a7), MODE(1) | RXACTIVE},            /* GMII2_RXCLK */
        {OFFSET(gpmc_a8), MODE(1) | RXACTIVE},            /* GMII2_RXD3 */
        {OFFSET(gpmc_a9), MODE(1) | RXACTIVE},            /* GMII2_RXD2 */
        {OFFSET(gpmc_a10), MODE(1) | RXACTIVE},            /* GMII2_RXD1 */
        {OFFSET(gpmc_a11), MODE(1) | RXACTIVE},            /* GMII2_RXD0 */
        {OFFSET(gpmc_wait0), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_CRS */
        {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE | PULLUP_EN},    /* GMII2_COL */
        {-1},
    };

    Thanks and regards

    Arndt

  • 0 in reply to Arndt Kritzner
    TI__Guru**** 393215 points
    Hi Arndt,
     
    Please add RXACTIVE for MDIO_CLK too. Most peripheral clocks are used for retiming inside the processor and need to be fed back from the pin.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 720 points

    Hi Biser, so I did, but this didn't change anything (for the moment).

  • 0 in reply to Arndt Kritzner
    TI__Intellectual 1340 points

    Hi Arndt,

    Did you try to use the TI U-boot from latest SDK v06.00? It has support especially for AM335x processors.

    You can find the LINUXEZSDK-AM335X here: http://www.ti.com/tool/linuxezsdk-sitara

    And here it is the release note for it:

    http://processors.wiki.ti.com/index.php/Sitara_SDK_6.00.00_Release_Notes

    Best regards,

    Vidin

  • 0 in reply to Vidin Tsonev-XID
    Intellectual 720 points

    Vidin,

    because I use a different pinmux and my board doesn't have a programmable PMIC and neither EEPROM nor NAND I have to compile this from sources with my board config. Just to compile for an unmodified am335x_evm board I had to patch drivers/net/cpsw.c, drivers/mtd/nand/omap_gpmc.c and arch/arm/cpu/armv7/omap-common/timer.c to include asm/arch/cpu.h.

    In the end I was able to compile an u-boot.img from your recommended SDK-sources, but the result is nearly the same as with my former used upstream sources:

    ...

    Net:   <ethaddr> not set. Validating first E-fuse MAC
    PHY reset timed out
    ...

    Best Regards

    Arndt

  • 0 in reply to Arndt Kritzner
    TI__Guru**** 393215 points
    Hi Arndt,
     
    Found this browsing the forum: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/238231.aspx. Might be related to your problem.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 720 points

    Hi Biser and Vidin,

    finally the PHY seems to be detected now. After adjusting CONFIG_PHY_ADDR to 1 (which is the devices default address) I don't get further error messages and link and activity LED are working. In my first try I didn't get an address via DHCP, but for today the improvement is not too bad.

    Thanks for your supportiveness.

    Kind Regards

    Arndt

  • 0 in reply to Arndt Kritzner
    Intellectual 545 points

    Hi !

    I have the gmii2 pin mux configured as 

    static struct module_pin_mux gmii2_pin_mux[] = {
    {OFFSET(gpmc_a0), MODE(1)}, /* GMII2_TXEN */
    {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* GMII2_RXDV */
    {OFFSET(gpmc_a2), MODE(1)}, /* GMII2_TXD3 */
    {OFFSET(gpmc_a3), MODE(1)}, /* GMII2_TXD2 */
    {OFFSET(gpmc_a4), MODE(1)}, /* GMII2_TXD1 */
    {OFFSET(gpmc_a5), MODE(1)}, /* GMII2_TXD0 */
    {OFFSET(gpmc_a6), MODE(1)| RXACTIVE}, /* GMII2_TXCLK */
    {OFFSET(gpmc_a7), MODE(1) | RXACTIVE| PULLUP_EN}, /* GMII2_RXCLK */
    {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* GMII2_RXD3 */
    {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* GMII2_RXD2 */
    {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* GMII2_RXD1 */
    {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* GMII2_RXD0 */
    {OFFSET(gpmc_wait0), MODE(1) | RXACTIVE }, /* GMII2_crs verify with john*/
    {OFFSET(gpmc_wpn), MODE(1) | RXACTIVE}, /* GMII2_rxer*/
    {OFFSET(gpmc_be1n), MODE(1) | RXACTIVE| PULLUP_EN},/* GMMI2_COL verify with john*/
    {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA*/
    {OFFSET(mdio_clk), MODE(0)| RXACTIVE| PULLUP_EN}, /* MDIO_MDC */
    {-1},

    };

    My phy is getting detected but i could not able to ping any ip.. My phy is MICREL 8081. I have included the 

    #define CONFIG_PHY_MICREL and #define CONFIG_PHY_ADDR 1.  I have verified from the WIreshark that no packets from the Board are sent to the host device.

    I am using the same cpsw data

    static struct cpsw_slave_data cpsw_slaves[] = {
    {
    .slave_reg_ofs = 0x208,
    .sliver_reg_ofs = 0xd80,
    .phy_id = 0,
    },
    {
    .slave_reg_ofs = 0x308,
    .sliver_reg_ofs = 0xdc0,
    .phy_id = 1,
    },
    };

    static struct cpsw_platform_data cpsw_data = {
    .mdio_base = CPSW_MDIO_BASE,
    .cpsw_base = CPSW_BASE,
    .mdio_div = 0xff,
    .channels = 8,
    .cpdma_reg_ofs = 0x800,
    .slaves = 1,
    .slave_data = cpsw_slaves,
    .ale_reg_ofs = 0xd00,
    .ale_entries = 1024,
    .host_port_reg_ofs = 0x108,
    .hw_stats_reg_ofs = 0x900,
    .mac_control = (1 << 5),
    .control = cpsw_control,
    .host_port_num = 0,
    .version = CPSW_CTRL_VERSION_2,
    };

    i was wondering if any one can has a working gmmi2 setting, please let me know what is the mistake i am doing??

    Thanks,

    harsha

  • 0 in reply to Harsha Kiran
    TI__Guru**** 393215 points
    Hi Harsha,
     
    Check that bit 5 GMII_EN in the corresponding MACCONTROL register is set to 1.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 545 points

    Hi Biser,

    We have verified the mac control register and is set to 1. But still the packets are not coming out of the processor. The CPSW stats are all 0.

    These are the settings we are using for GMMi2

    static struct cpsw_slave_data cpsw_slaves[] = {

    {
    .slave_reg_ofs = 0x308,
    .sliver_reg_ofs = 0xdc0,
    .phy_id = 1,
    },
    };

    static struct cpsw_platform_data cpsw_data = {
    .mdio_base = CPSW_MDIO_BASE,
    .cpsw_base = CPSW_BASE,
    .mdio_div = 0xff,
    .channels = 8,
    .cpdma_reg_ofs = 0x800,
    .slaves = 1,
    .slave_data = cpsw_slaves,
    .ale_reg_ofs = 0xd00,
    .ale_entries = 1024,
    .host_port_reg_ofs = 0x108,
    .hw_stats_reg_ofs = 0x900,
    .mac_control = (1 << 5),
    .control = cpsw_control,
    .host_port_num = 0,
    .version = CPSW_CTRL_VERSION_2,
    };

    Thanks,

    harsha