Not able to perform DDR3 S\W write leveling on our design as per the guidelines on wiki

Praveen Kajjam

Other Parts Discussed in Thread: AM3358, TPS51200

Hi,

We are using same DDR3 memory MT41K256M16HA-125IT_E as used in BBB in our design. We followed the instruction for S\W write leveling provided with below link:

http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

Also we referred the instructions provided for BBB design at below link:

http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack#Lab_Steps

We got the following register values after entering the trace length values in "RatioSeed_AM335x_boards" spreadsheetBut when we run the GEL file with the CCS on our board i am always reading "zeros" for the register values as below:

Seed values used in CCS code
DATAx_PHY_RD DQS_SLAVE_RATIO	40
DATAx_PHY_FIFO_WE_SLAVE_RATIO	9D
DATAx_PHY_WR DQS_SLAVE_RATIO	8
DATAx_PHY_WR_DATA_SLAVE_RATIO_0
Register value
CMDx_PHY_CTRL_SLAVE_RATIO	80

Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
0

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
40

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
9D

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
08

***************************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DQS_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
DATA_PHY_WR_DATA_SLAVE_RATIO 0x000 | 0x000 | 0x000 | 0x000
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 0
wr_data_range = 0

Optimal values have been found!!

===== END OF TEST =====

I am using XDS100V2-ARM emulator with CCS Evaluation Version: 6.0.1.00040

Can someone help me to identify the root cause for fixing this issue?

As of now our DDR3 interface working fine with the register values calculated for BBB but these register values might be generated from the different electrical trace lengths of CK & DQs routed on BBB. We want actual values generated on our design.

Thanks & Regards,

Praveen Kajjam.

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi Praveen,

I will ask somebody from the factory team to look into this.

0 Biser Gatchev-XID over 10 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

Can you try with INVERT_CLKOUT=1?

0 Praveen Kajjam over 10 years ago in reply to Biser Gatchev-XID

Intellectual 365 points

As per my PCB design DDR_CK trace length is 2.02 inches and DDR_DQSx trace length is 1.535 inches. As per the recommendation from the Ratio Seed spreadsheet i entered '0' for PHY_INVERT_CLKOUT.

But just to give a try i entered '1' for PHY_INVERT_CLKOUT and got below values for 400MHz clock.

Seed values used in CCS code
DATAx_PHY_RD DQS_SLAVE_RATIO	40
DATAx_PHY_FIFO_WE_SLAVE_RATIO	11D
DATAx_PHY_WR DQS_SLAVE_RATIO	88
DATAx_PHY_WR_DATA_SLAVE_RATIO_0

When i run the GEL file with these values also i don't see any difference in the result:

Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
1

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
40

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
11D

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
88

Optimal values have been found!!

===== END OF TEST =====

Thanks & Regards,

Praveen Kajjam

0 Biser Gatchev-XID over 10 years ago in reply to Praveen Kajjam

TI__Guru**** 393215 points

Hi,

Factory team has asked if you can post GEL file being used for SW leveling and Amy other relevant files used during leveling? You can attach them to a post using the paper clip icon (insert file) on the tool menu above your post.

0 Praveen Kajjam over 10 years ago in reply to Biser Gatchev-XID

Intellectual 365 points

Hi Biser,

Find the attached documents i used for S\E write leveling.

3884.RatioSeed_AM335x_boards.xlsx

4162.AM335x_DDR_register_calc_tool.xlsx

4863.AM3358_StarterKit.zip

2425.AM3358_StarterKit_Modified.zip

3542.DDR3_slave_ratio_search_auto.zip

4263.4Gb_1_35V_DDR3L.pdf

Notes:

File "AM3358_StarterKit" is the original GEL file.

File "AM3358_StarterKit_Modified" is modified GEL file with timing register values calculated through "AM335x_DDR_register_calc_tool" xlsx file.

File "DDR3_slave_ratio_search_auto" is oroginal .out file from wiki.

File "AM335x_DDR_register_calc_tool" is used to generated to timing register values with DDR3 chip used. Refer the worksheet "AM335x-DDR3_400MHz" correct data.

File" RatioSeed_AM335x_boards" used with PCB trace length information. Refer the worksheet "DDR3_400MHz" for correct data.

File "4Gb_1_35V_DDR3L" DDR3 datasheet we are using. Part number is "MT41K256M16HA-125IT_E".

Please let me know if the you need our design schematics.

Thanks & Regards,

Praveen Kajjam.

0 Praveen Kajjam over 10 years ago in reply to Praveen Kajjam

Intellectual 365 points

Hello Biser,

Did you here anything back from factory on the GEL file i am using?

Thanks & Regards,

Praveen Kajjam.

0 Biser Gatchev-XID over 10 years ago in reply to Praveen Kajjam

TI__Guru**** 393215 points

No reply yet. This thread will be updated when there is feedback.

0 Brad Griffis over 10 years ago in reply to Biser Gatchev-XID

TI__Guru*** 125430 points

Can you post a skew report with all the DDR signal lengths for your PCB?

0 Praveen Kajjam over 10 years ago in reply to Brad Griffis

Intellectual 365 points

Hello Brad,

Find the attached spreadsheet with the trace length report. All the DDR3 related signals are highlighted in yellow.

Thanks & Regards,

Praveen Kajjam

.8015.Trace Length Report.xlsx

0 Brad Griffis over 10 years ago in reply to Praveen Kajjam

TI__Guru*** 125430 points

Does your DDR3 interface work reliably? The software leveling is there to give you some added margin, but it should be fully operational as a starting point.

Looking at your skew report, the only thing that stood out was that DDR_ODT was only 1335.54 mils. That signal belongs to the ADDR_CTL. It should be closer to 2018 mils (the average of all the other ADDR_CTL signals). I don't know if this is specifically why you're seeing you're issue, but it's something you should correct.

If you can post some pages from your schematic showing the DDR hookup I would like to see how it's done. It looks like you've implemented VTT on the board. This isn't necessary for a simple point-to-point hookup (e.g. single 16-bit DDR implementation). There are subtle ways for this to go wrong so I wanted to have a look.

0 Praveen Kajjam over 10 years ago in reply to Brad Griffis

Intellectual 365 points

Hello Brad,

As of now we are using the S\W write leveling implemented register values from the Beagle Bone Black and our design working reliably and performance is stable. We almost completed 70% of our development on the prototype without any issues seen related to DDR3 memory.

I know that we are running with a risk using BBB register values. We are trying hard to mitigate the risk by running S\W write leveling on our board to get hold on the timing margins. But not yet successful.

Regarding DDR_ODT trace, i thought it is just a static signal either enable or disable the ODT feature of the memory. That might be the reason we might miss to match its trace length with other ADDR_CTL signals. I will take care of this in next PCB revision.

Yes we had implemented the VTT regulator in our design as per schematics checklist guideline on Wiki page. This is the only difference between our design and Beagle Bone Black. It might play a vital role on our S\W write leveling issue. Need your feedback related to VTT after your schematics review.

During our schematics design phase entire schematics got reviewed by TI application team (Biser Gatchev) but didn't receiver any comments related to VTT implementation. However I am attaching the design schematics here for your review. Refer page 2 & 7 for DDR3 interface design. We are planning to start our production design in Dec 2014. We need to find out a resolution for this issue at the earliest.

Please let me know if you need any additional information. Thanks in advance for you extended support.

Thanks & Regards,

Praveen Kajjam.

0 Praveen Kajjam over 10 years ago in reply to Praveen Kajjam

Intellectual 365 points

Hello Brad,

Want to share another input with you regarding VTT termination. Below is the comment on termination resistor value from Biser during schematics review but we could not implement it. Not sure will the termination value have any impact on S\W write leveling issue.

#8
Page:7	Level:
Section: Vtt Termination Resistors	Originator: Biser Gatchev
TI Comments: All Vtt termination resistors should be 51Ohm, not 33Ohm. R22 and R23 should be 49.9Ohm 1%. Termination should be removed on DDR_RESET.
Corrective actions: TI reference designs use 33 Ohms. Will keep the same and tweak the value during debug and finalize optimum value. Termination for DDR_RESET is already depopulated.
Customer feedback : No Action.

Thanks & Regards,

Praveen Kajjam.

0 Brad Griffis over 10 years ago in reply to Praveen Kajjam

TI__Guru*** 125430 points

Praveen Kajjam said:
As of now we are using the S\W write leveling implemented register values from the Beagle Bone Black and our design working reliably and performance is stable. We almost completed 70% of our development on the prototype without any issues seen related to DDR3 memory.

Instead of using the seed values from the spreadsheet can you use the settings from the BeagleBone Black as your "seed"? The point of the seed is just to have functional values in there. Since everything sounds to be working just fine using those values from the BBB, that should be fine. The seed value doesn't influence the outcome. We just need to start with a working value and then we sweep to determine at what point it breaks in each direction and then choose the value in the middle. Hopefully that will get you a proper result! Let me know how it goes...

Praveen Kajjam said:
However I am attaching the design schematics here for your review. Refer page 2 & 7 for DDR3 interface design.

Mostly looks fine. Unless I'm overlooking it somewhere, I don't see any output caps on the TPS51200 "VO" pin. You are supposed to have a minimum of 20uF of caps, with the recommendation being to add three 10uF caps. This may again not have anything to do with your leveling issue, though it is another thing that you should correct in your next revision.

0 Praveen Kajjam over 10 years ago in reply to Brad Griffis

Intellectual 365 points

Hello Brad,

On the first point i am not clear about your suggestion. Can you please elaborate the same?

On the second point i have already three 10uF capacitors loaded on "VO" pin of the VTT regulator. They are placed on top middle of the schematics sheet 7. Reference Desiccators are C110, C111 and C112.

Thanks & Regards,

Praveen Kajjam

0 Brad Griffis over 10 years ago in reply to Praveen Kajjam

TI__Guru*** 125430 points

Praveen Kajjam said:
On the first point i am not clear about your suggestion. Can you please elaborate the same?

Try this:

Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
0

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
38

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
94

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
44

Those are the BeagleBone Black values.

0 Brad Griffis over 10 years ago in reply to Praveen Kajjam

TI__Guru*** 125430 points

Praveen Kajjam said:
On the second point i have already three 10uF capacitors loaded on "VO" pin of the VTT regulator. They are placed on top middle of the schematics sheet 7. Reference Desiccators are C110, C111 and C112.

Sorry, missed that. Looks good!

0 Praveen Kajjam over 10 years ago in reply to Brad Griffis

Intellectual 365 points

Hello Brad,

Tried with BBB values but dont see any difference in the result.

[CortxA8]
Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
0

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
38

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
94

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
44

Optimal values have been found!!

===== END OF TEST =====

Another thing i would like to reiterate is on the difference between BBB DDR3 implementation and our design. BBB has not implemented VVT regulator and VTT termination resistors but we have implemented this on our design. Do you want me to depopulate VTT related components from our board and try write leveling? On the other hand this may call for signal integrity issues due to open traces on the PCB for the address lines due to depopulation of VTT related components.

Thanks & Regards,

Praveen Kajjam

0 Brad Griffis over 10 years ago in reply to Praveen Kajjam

TI__Guru*** 125430 points

Let's try an alternate method... One of my colleagues in China actually created a bootable version of the software leveling tool (i.e. an MLO file) and doesn't require JTAG. You simply boot from the MLO, enter all your timing parameters through the UART console, and then it prints out the leveling results to the console. The MLO and a User Guide (in English!) can be found here on our Chinese forum:

http://www.deyisupport.com/question_answer/dsp_arm/sitara_arm/f/25/t/53263.aspx

I've had other customers that were experiencing issues with using JTAG based software leveling that this MLO worked better for them. Please try it out and let me know how it goes. Hopefully your hardware is compatible, i.e. boot from MMC and interact through UART console.

0 Praveen Kajjam over 10 years ago in reply to Brad Griffis

Intellectual 365 points

Hello Brad,

I am able to run this alternate method of bootable version of the S\W write leveling and found no different results than the JTAG method. Please find the below results for your review.

AM335x DDR3 Software Leveling -- Version: Beta 3.0
-- Copyright: Texas Instruments China Local Team
*************************** Program Start********************************

Please input the AM335x EMIF Timing Configuration:

-- AM335x Default EMIF Timing configuration (for StarterKit EVM) --

DDR3_EMIF_SDRAM_TIM_1 : 0x0888A39B

DDR3_EMIF_SDRAM_TIM_2 : 0x26337FDA

DDR3_EMIF_SDRAM_TIM_3 : 0x501F830F

DDR3_EMIF_SDRAM_CONFIG : 0x61C04AB2

Your choice: 1. Use the default one; 2. Input your own one.

2
Please Choose The DDR3 Frequency: 1. 303MHz; 2. 400MHz.

2
DDR3 Frequency is Set at 400MHz!

Please input your DDR3_EMIF_SDRAM_TIM_1 conifguration (in Hex) :

0AAAD4DB
Please input your DDR3_EMIF_SDRAM_TIM_2 conifguration (in Hex) :

266B7FDA
Please input your DDR3_EMIF_SDRAM_TIM_3 conifguration (in Hex) :

501F867F
Please input your DDR3_EMIF_SDRAM_CONFIG conifguration (in Hex) :

61C05332

Your input EMIF Timing configuration --

DDR3_EMIF_SDRAM_TIM_1 : 0xAAAD4DB

DDR3_EMIF_SDRAM_TIM_2 : 0x266B7FDA

DDR3_EMIF_SDRAM_TIM_3 : 0x501F867F

DDR3_EMIF_SDRAM_CONFIG : 0x61C05332

Please Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet :

0
Please Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window :

40
Please Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window :

9D
Please Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window :

08
Please Enter the Seed PHY_CTRL_SLAVE_RATIO Value in Hex :

80
The ratio seeds for the DDR3 Software Leveling :

invert_clkout = 0x0

RD_DQS_RATIO_VAL = 0x40

FIFO_WE_SLAVE_RATIO = 0x9D

WR_DQS_SLAVE_RATIO = 0x8

PHY_CTRL_SLAVE_RATIO = 0x80

The Slave Ratio Search Program Values are...
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO is :0x0
DATA_PHY_FIFO_WE_SLAVE_RATIO is : 0x0
DATA_PHY_WR_DQS_SLAVE_RATIO is : 0x0
DATA_PHY_WR_DATA_SLAVE_RATIO is : 0x0
***************************************************************
rd_dqs_range = 0
fifo_we_range = 0
wr_dqs_range = 0
wr_data_range = 0

Optimal values have been found!!

***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO is :0x0
DATA_PHY_FIFO_WE_SLAVE_RATIO is : 0x0
DATA_PHY_WR_DQS_SLAVE_RATIO is : 0x0
DATA_PHY_WR_DATA_SLAVE_RATIO is : 0x0
***************************************************************

===== END OF TEST =====
DDR3 software leveling done!

Thanks & Regards,

Praveen Kajjam

0 Praveen Kajjam over 10 years ago in reply to Praveen Kajjam

Intellectual 365 points

Hello Brad,

Any further suggestions on this issue?

Yesterday i procured on BBB and tried S\W write leveling experiment with that. Initially it worked fine for couple of iterations and able to see the optimum register values.

Later when i tried today it continuously giving below error. Not sure what went wrong. I am just trying to debug this issue.

Do you want me to remove the VTT regulator and termination resistors as like BBB and re-run the S\W write leveling procedure?

CortxA8: Output: **** AM3358_SK Initialization is in progress ..........
CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress .........
CortxA8: GEL: Error while executing OnTargetConnect(): Target failed to read 0x44E10040 at (*((unsigned int *) (0x44E10000+0x40))>>22) [AM3358_StarterKit.gel:381] at GetInputClockFrequency() [AM3358_StarterKit.gel:452] at ARM_OPP100_Config() [AM3358_StarterKit.gel:372] at AM3358_SK_Initialization() [AM3358_StarterKit.gel:358] at OnTargetConnect() .

0 Praveen Kajjam over 10 years ago in reply to Praveen Kajjam

Intellectual 365 points

Hello Brad,

Finally i found the root cause and fixed the issue. S\W write leveling works fine with my design now. Issue is with VTT enable. GEL file has code to enable the VTT regulator through GPIO pin which is a different GPIO pin in our design. I jut made a force enable of that and it started working. See the screenshot below.

Thanks for your support for all these days.

[CortxA8]
Enter the PHY_INVERT_CLKOUT value (0 or 1) from the spreadsheet
0

Enter the Seed RD_DQS_SLAVE_RATIO Value in Hex to search the RD DQS Ratio Window
40

Enter the Seed FIFO_WE_SLAVE_RATIO Value in Hex to search the RD DQS Gate Window
9D

Enter the Seed WR_DQS_SLAVE_RATIO Write DQS Ratio Value in Hex to search the Write DQS Ratio Window
08

***************************************************************
The Slave Ratio Search Program Values are...
***************************************************************
PARAMETER MAX | MIN | OPTIMUM | RANGE
***************************************************************
DATA_PHY_RD_DQS_SLAVE_RATIO 0x06a | 0x002 | 0x036 | 0x068
DATA_PHY_FIFO_WE_SLAVE_RATIO 0x152 | 0x000 | 0x0a9 | 0x152
DATA_PHY_WR_DQS_SLAVE_RATIO 0x041 | 0x000 | 0x020 | 0x041
DATA_PHY_WR_DATA_SLAVE_RATIO 0x07d | 0x00d | 0x045 | 0x070
***************************************************************
rd_dqs_range = 36
fifo_we_range = a9
wr_dqs_range = 20
wr_data_range = 45