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Linux/AM3352: Triggering DMA from XDMA pin

Part Number: AM3352

Tool/software: Linux

Hello,

I can not get DMA transfers to get triggered with GPIO pin or XDMA pin. We use kernel 4.4.41 from TI SDK. We have external device which should trigger DMA transfers. It works if we register interrupt handler for GPIO in Linux and in the interrupt handler DMA transfers are software triggered as memory to memory transfers. But interrupt handling takes to much and jitter is unacceptable so we want to trigger DMA directly. There are some related threads on e2e :

https://e2e.ti.com/support/arm/sitara_arm/f/791/p/593810/2203586 

abcd {
compatible = "abcd";
status = "okay";
dmas = <0x34 20 0 29>;
dma-names = "dma_test";
};

0x34 is reference to crossbar (in this config we wanted to trigger DMA with XDMA_EVENT_INTR1 pin)

we also tried with 

dmas = <0x2d 22 0>;

where 0x2d is reference to edma (in this config we wanted to trigger DMA with GPIO0_7 pin)

we get the channel, for which we have interfaces for device_prep_slave_sg (no reference to mem2mem copy interface - as in the thread mentioned above). So we configure transaction for dma with prep_slave_sg, then we submit transaction but it is never executed. We would like to trigger it with external pin but it seems that something is missing. 

Pins are configured in appriopriate mode for XDMA and GPIO but it seems that events are never registered. When I dump ER register of EDMA3CC I do not see any changes in corresponding bits for events. TRM says that events are registered even if they are not enabled - should I see status change in ER register for any GPIO change? . Is there some configuration that I am missing to trigger DMA from external device? 

Best regards.

  • The software team have been notified. They will respond here.
  • One more thing that I noticed: if I configure crossbar to map xdma intr1 pin to channel 20 (channels 20, 21 are configured in default TI dts for memcpy transfers)
    dmas = <0x34 20 0 29>;
    then instead of device_prep_slave_sg I get pointer to device_prep_dma_memcpy. Which would be OK, but still the transfer is not triggered. With the crossbar configuration dma transfer is not done. The same configuration but after requesting DMA_MEMCPY : transfers can be triggered in software. Anyway no matter which configuration I use - I can not get DMA transfers to be triggered from some external pin. For XDMA pin I just configure it as input in mode 0. For GPIO0 pin I configure it as input in MODE7 (GPIO0_7).

    I can see that in EER register bit for EVENT20 is not enabled, for other configs (like triggering from GPIO0) the event is also not enabled. I can only see bit for URXEVT0 enabled...
  • Hi Jacek,

    GPIO0 EDMA event (GPIOEVT0, #22) is directly mapped, no need to configure the cross bar, see AM335x TRM, section 11.3.19 EDMA Events

    Which physical pin you are using for GPIO0 EDMA? Do you use B15(ZCE)/D14(ZCZ) XDMA_EVENT_INTR1.gpio0_20? Or E18(ZCE)/C18(ZCZ) ECAP0_IN_PWM0_OUT.gpio0_7 pin?

    See if the below e2e threads will be in help:

    e2e.ti.com/.../209013
    e2e.ti.com/.../178492
    e2e.ti.com/.../188447

    e2e.ti.com/.../581725
    e2e.ti.com/.../580713

    github.com/.../9b5005a521290d3cb3725b5801a85a4dac13d174
    github.com/.../01b5e914e58e8bdfce2244e6a38578f041f9702d

    Regards,
    Pavel
  • Hello,

    thank you for the links provided. I am aware of direct mapping of GPIO0 - unfortunatelly I was not able to trigger DMA transfer with this pin. This is why I also tried with XDMA_EVENT_INTR1 for which crossbar has to be configured. I used D14 for XDMA_EVENT_INTR1 test and C18 for GPIO test. Now the configuration that seems to be responsive is 

       dmas = <0x34 20 0 29>;

    which is mapping of indirect XDMA_EVENT_INTR1 to Open 20 event (which is defined in TI DTS for memory transfers, right?). This makes TPCC_EVT_MUX_20_23 to contain 0x0000001d which is according to the configuration. After configuration of XINTR1 pin as MODE0 input - dma memory to memory transfer is triggered. With this config requesting DMA_SLAVE in the driver returns pointer to device_prep_dma_memcpy. OK. So in this way it seems I am able to trigger DMA transfers with XINTR1 external pin. For this configuration I have additional question: after I obtained dma channel for memcpy - can I use it exclusively for my transfers as long as I do not free it?

    Still I am not able to trigger DMA transfer with GPIO pin - would this recipe be enough:

    - configure device tree to use dmas = <0x2d 22 0>; (0x2d is phandle for edma). 22 is for GPIOEVT0
    - GPIO0_7 is configured as input GPIO (MODE7)


    in the driver:
    - request DMA_SLAVE channel
    - for such configuration I expect to have device_prep_slave_sg and _cyclic interfaces returned - this is what I get really - with such configuration in DTS I get channel which has no MEM2MEM property set - so no memory to memory interface is available.
    - prepare dma transfer - this should wait for an event on gpio0_7 pin, after it is triggered dma should start and callback should be called.

    Is this correct way of doing this or am I missing something? For now with above config I can not trigger DMA transfer with GPIO0_7 pin :-( GPEVT driver that you linked seems to work this way so I guess I must be missing something basic here. Anyway if you see some misconfiguration or have any more hints they would be much appreciated.

     

     

  • I applied configuration from gpevt sample driver and I was able to trigger DMA transfer from GPIO0_7 pin. For some reason mapping of GPIO2 event was not succesful:

    dma-router: Invalid XBAR event number: 32

    do you know the reason? Should I open another thread for this question, if yes then I will mark this thread as solved as it seems I am able now to trigger DMA transfers from both GPIO (though GPIO2 seems unavailable for now) and XINTR pins.

    Thank you for the links provided - they were very helpful.

  • Hi Jacek,

    See AM335x TRM, section 11.3.19 EDMA Events

    GPIO0 EDMA event (GPIOEVT0, #22) is directly mapped, no need to configure the cross bar - Table 11-23. Direct Mapped

    GPIO2 EDMA event (GPIOEVT2, #32) is mapped through the crossbar - Table 11-24. Crossbar Mapped

    Please close/verify/resolve this thread and open new one regarding GPIOEVT2 crossbar (XBAR) event config.

    Regards,
    Pavel