Linux/AM3358: DP83867 PHY issue

Shiami

Prodigy 70 points

Part Number: AM3358

Tool/software: Linux

Hi,

some issues in my custom board with dp83867, kernel cannot found phy device

in kernel log seems fine

[ 1.100566] libphy: Fixed MDIO Bus: probed
[ 1.164521] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[ 1.170670] libphy: 4a101000.mdio: probed
[ 1.175400] cpsw 4a100000.ethernet: Detected MACID = 98:5d:ad:7b:c3:5e

but in initial eth0 cannot found phy device

[ 6.349598] net eth0: initializing cpsw version 1.12 (0)
[ 6.356709] libphy: PHY 4a101000.mdio:00 not found
[ 6.361527] net eth0: phy 4a101000.mdio:00 not found on slave 0
[ 6.368144] libphy: PHY 4a101000.mdio:01 not found
[ 6.373016] net eth0: phy 4a101000.mdio:01 not found on slave 1

below is ifconfig response:

eth0 Link encap:Ethernet HWaddr 98:5D:AD:7B:C3:5E
inet addr:10.1.1.100 Bcast:0.0.0.0 Mask:255.255.255.0
UP BROADCAST MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)
Interrupt:174

lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:65536 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)

here is my dts about network

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
    status = "okay";

	dp83867_0: ethernet-phy@0 {
        reg = <0>;
        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
        ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
        ti,min-output-impedance;
        ti,dp83867-rxctrl-strap-quirk;
    };
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <0>;
	phy-mode = "rgmii-txid";
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "rgmii-txid";
};

over 7 years ago

0 Schuyler Patton over 7 years ago

TI__Mastermind 40570 points

Hi,

Here a checklist that if you could please follow to help with understanding where the issue might be on your board. Also please attach the results requested to this post. Also please attach log files or ethtool results individually so they are easier to pull up. Attaching compressed files is a little more challenging for everybody to look at.

processors.wiki.ti.com/.../5x_CPSW

Is the ip address static? I assuming it is since there are not any packet count showing for RX/TX where DHCP traffic would have occurred.

The checklist will ask for ethtool results that indicate whether or not a link is detected. Since the PHY is not detected by the MDIO driver during boot then most likely ethtool will not return meaningful data.

Also mentioned in the checklist is using wireshark to look for any packets that might be sent from or should have been received. Checking to see if packets are least coming is a good first step.

Best Regards,
Schuyler

0 Shiami over 7 years ago in reply to Schuyler Patton

Prodigy 70 points

Hi,

After check DP83867's reset_n pin, it could be detect in mdio bus, and boot log as below

[ 1.164483] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[ 1.170637] libphy: 4a101000.mdio: probed
[ 1.175510] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver unknown
[ 1.184211] cpsw 4a100000.ethernet: Missing slave[1] phy_id property
[ 1.190714] cpsw 4a100000.ethernet: Detected MACID = 98:5d:ad:7b:c3:5e

[ 6.138124] net eth0: initializing cpsw version 1.12 (0)
[ 6.224995] net eth0: phy found : id is : 0x79497949
[ 6.230086] libphy: PHY not found
[ 6.233505] net eth0: phy not found on slave 1

but problem is still can not found driver, where can i check ?
thank you

0 Schuyler Patton over 7 years ago in reply to Shiami

TI__Mastermind 40570 points

Hi,

I think you are on the right path concerning making sure there is a proper reset to the PHY. Looking at the at this line is reporting the PHY ID found,

net eth0: phy found : id is : 0x79497949

This is not the correct PHY ID for the PHY selected, looking at the data sheet it should be 080028h. Once you get this number to appear in the boot log look at the kernel configuration for this PHY family to make sure it is configured to be built with the kernel.

Best Regards,
Schuyler

0 Shiami over 7 years ago in reply to Schuyler Patton

Prodigy 70 points

Hi,

Changing the dts, i found the main problem that phy mask is incorrect it shound be 0xfffffff0 (DP83867)

but alway get 0xfffffffe.

In the kernel had add supoort DP83867 (CONFIG_DP83867_PHY=y), but still not wor

[ 1.184483] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[ 1.190608] davinci_mdio 4a101000.mdio: detected phy mask fffffffe
[ 1.197570] libphy: 4a101000.mdio: probed
[ 1.201609] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver unknown
[ 1.210411] cpsw 4a100000.ethernet: Missing slave[1] phy_id property
[ 1.216938] cpsw 4a100000.ethernet: Detected MACID = 98:5d:ad:7b:c3:5e

attached file have dts and defconfig

dts file:

Fullscreen 4118.am335x-evm.dts.txt Download

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/net/ti-dp83867.h>

/ {
	model = "TI AM335x EVM";
	compatible = "ti,am335x-evm", "ti,am33xx";

	cpus {
		cpu@0 {
			cpu0-supply = <&vdd1_reg>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	vbat: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "vbat";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};

	lis3_reg: fixedregulator@1 {
		compatible = "regulator-fixed";
		regulator-name = "lis3_reg";
		regulator-boot-on;
	};

/*
	leds {
                pinctrl-names = "default";
                pinctrl-0 = <&user_leds_s0>;

                compatible = "gpio-leds";

                led@1 {
                        label = "evmsk:green:heartbeat";
                        gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
                        default-state = "on";
                };
        };
*/

	backlight {
		compatible = "pwm-backlight";
		pwms = <&ecap2 0 50000 0>;
		brightness-levels = <0 51 53 56 62 75 101 152 255>;
		default-brightness-level = <1>;
	};

	panel {
		compatible = "ti,tilcdc,panel";
		status = "okay";
		panel-info {
			ac-bias           = <255>;
			ac-bias-intrpt    = <0>;
			dma-burst-sz      = <16>;
			bpp               = <16>;
			fdd               = <0x80>;
			sync-edge         = <0>;
			sync-ctrl         = <1>;
			raster-order      = <0>;
			fifo-th           = <0>;
		};

		display-timings {
			/*
			1024x600p62 {
				clock-frequency = <60000000>;
				hactive = <1024>;
				vactive = <600>;
				hfront-porch = <160>;
				hback-porch = <140>;
				hsync-len = <20>;
				vback-porch = <20>;
				vfront-porch = <12>;
				vsync-len = <3>;
				hsync-active = <1>;
				vsync-active = <1>;
			};*/

			/*This is the timing for HDMI&VGA*/
			1024x768p62 {
				clock-frequency = <80000000>;
				hactive = <1024>;
				vactive = <768>;
				hfront-porch = <18>;
				hback-porch = <297>;
				hsync-len = <53>;
				vfront-porch = <3>;
				vback-porch = <35>;
				vsync-len = <6>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <1>;
			};
		};
	};

};

&am33xx_pinmux {
	pinctrl-names = "default";
	pinctrl-0 = < >;


	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
		>;
	};
#if 0
	i2c1_pins_default: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			0x158 (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_d1.i2c1_sda */
			0x15c (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_cs0.i2c1_scl */
		>;
	};

	i2c1_pins_sleep: i2c1_pins_sleep {
		pinctrl-single,pins = <
			0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* spi0_d1.i2c1_sda */
			0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* spi0_cs0.i2c1_scl */
		>;
	};
#endif
	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
		>;
	};
#if 0
	uart1_pins_default: pinmux_uart1_pins_default {
		pinctrl-single,pins = <
			0x178 (PIN_INPUT | MUX_MODE0)			/* uart1_ctsn.uart1_ctsn */
			0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_rtsn.uart1_rtsn */
			0x180 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
			0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) 	/* uart1_txd.uart1_txd */
		>;
	};

	uart1_pins_sleep: pinmux_uart1_pins_sleep {
		pinctrl-single,pins = <
			0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x17C (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x180 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x184 (PIN_INPUT_PULLDOWN | MUX_MODE7)
		>;
	};


	ecap2_pins_default: backlight_pins {
		pinctrl-single,pins = <
			0x19c 0x04	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
		>;
	};

	ecap2_pins_sleep: ecap2_pins_sleep {
		pinctrl-single,pins = <
			0x19c  (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
		>;
	};
#endif
	cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
			0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
		>;
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */
			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
		>;
	};

	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
		>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
		pinctrl-single,pins = <
			/* MDIO reset value */
			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
		>;
	};

	mmc1_pins_default: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat3.mmc0_dat3 */
			0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat2.mmc0_dat2 */
			0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat1.mmc0_dat1 */
			0x0FC (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat0.mmc0_dat0 */
			0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_clk.mmc0_clk */
			0x104 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_cmd.mmc0_cmd */
			0x1A4 (PIN_INPUT_PULLUP | MUX_MODE7)    /* mcasp0_fsr.gpio3_19 */
		>;
	};

	mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
		pinctrl-single,pins = <
			0x0F0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x0F4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x0F8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x0FC (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x1A4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
		>;
	};

#if 0
	mmc2_pins_default: pinmux_mmc2_pins {
                pinctrl-single,pins = <
                        0x000 (PIN_INPUT_PULLUP | MUX_MODE1)    /* gpmc_ad0.mmc1_dat0 */
                        0x004 (PIN_INPUT_PULLUP | MUX_MODE1)    /* gpmc_ad1.mmc1_dat1 */
                        0x008 (PIN_INPUT_PULLUP | MUX_MODE1)    /* gpmc_ad2.mmc1_dat2 */
                        0x00c (PIN_INPUT_PULLUP | MUX_MODE1)    /* gpmc_ad3.mmc1_dat3 */
                        0x010 (PIN_INPUT_PULLUP | MUX_MODE1)    /* gpmc_ad4.mmc1_dat4 */
                        0x014 (PIN_INPUT_PULLUP | MUX_MODE1)    /* gpmc_ad5.mmc1_dat5 */
                        0x018 (PIN_INPUT_PULLUP | MUX_MODE1)    /* gpmc_ad6.mmc1_dat6 */
                        0x01c (PIN_INPUT_PULLUP | MUX_MODE1)    /* gpmc_ad7.mmc1_dat7 */
                >;
        };

        mmc2_pins_sleep: pinmux_mmc2_pins_sleep {
                pinctrl-single,pins = <
                        0x000 (PIN_INPUT_PULLDOWN | MUX_MODE1)    /* gpmc_ad0.mmc1_dat0 */
                        0x004 (PIN_INPUT_PULLDOWN | MUX_MODE1)    /* gpmc_ad1.mmc1_dat1 */
                        0x008 (PIN_INPUT_PULLDOWN | MUX_MODE1)    /* gpmc_ad2.mmc1_dat2 */
                        0x00c (PIN_INPUT_PULLDOWN | MUX_MODE1)    /* gpmc_ad3.mmc1_dat3 */
                        0x010 (PIN_INPUT_PULLDOWN | MUX_MODE1)    /* gpmc_ad4.mmc1_dat4 */
                        0x014 (PIN_INPUT_PULLDOWN | MUX_MODE1)    /* gpmc_ad5.mmc1_dat5 */
                        0x018 (PIN_INPUT_PULLDOWN | MUX_MODE1)    /* gpmc_ad6.mmc1_dat6 */
                        0x01c (PIN_INPUT_PULLDOWN | MUX_MODE1)    /* gpmc_ad7.mmc1_dat7 */
                >;
        };
#endif

	lcd_pins_default: lcd_pins_default {
		pinctrl-single,pins = <
			0xa0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data0.lcd_data0 */
			0xa4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data1.lcd_data1 */
			0xa8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data2.lcd_data2 */
			0xac (PIN_OUTPUT | MUX_MODE0)		/* lcd_data3.lcd_data3 */
			0xb0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data4.lcd_data4 */
			0xb4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data5.lcd_data5 */
			0xb8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data6.lcd_data6 */
			0xbc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data7.lcd_data7 */
			0xc0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data8.lcd_data8 */
			0xc4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data9.lcd_data9 */
			0xc8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data10.lcd_data10 */
			0xcc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data11.lcd_data11 */
			0xd0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data12.lcd_data12 */
			0xd4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data13.lcd_data13 */
			0xd8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data14.lcd_data14 */
			0xdc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data15.lcd_data15 */
			0xe0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_vsync.lcd_vsync */
			0xe4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_hsync.lcd_hsync */
			0xe8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_pclk.lcd_pclk */
			0xec (PIN_OUTPUT | MUX_MODE0)		/* lcd_ac_bias_en.lcd_ac_bias_en */
		>;
	};

	lcd_pins_sleep: lcd_pins_sleep {
		pinctrl-single,pins = <
			0xa0 (PULL_DISABLE | MUX_MODE7)		/* lcd_data0.lcd_data0 */
			0xa4 (PULL_DISABLE | MUX_MODE7)		/* lcd_data1.lcd_data1 */
			0xa8 (PULL_DISABLE | MUX_MODE7)		/* lcd_data2.lcd_data2 */
			0xac (PULL_DISABLE | MUX_MODE7)		/* lcd_data3.lcd_data3 */
			0xb0 (PULL_DISABLE | MUX_MODE7)		/* lcd_data4.lcd_data4 */
			0xb4 (PULL_DISABLE | MUX_MODE7)		/* lcd_data5.lcd_data5 */
			0xb8 (PULL_DISABLE | MUX_MODE7)		/* lcd_data6.lcd_data6 */
			0xbc (PULL_DISABLE | MUX_MODE7)		/* lcd_data7.lcd_data7 */
			0xc0 (PULL_DISABLE | MUX_MODE7)		/* lcd_data8.lcd_data8 */
			0xc4 (PULL_DISABLE | MUX_MODE7)		/* lcd_data9.lcd_data9 */
			0xc8 (PULL_DISABLE | MUX_MODE7)		/* lcd_data10.lcd_data10 */
			0xcc (PULL_DISABLE | MUX_MODE7)		/* lcd_data11.lcd_data11 */
			0xd0 (PULL_DISABLE | MUX_MODE7)		/* lcd_data12.lcd_data12 */
			0xd4 (PULL_DISABLE | MUX_MODE7)		/* lcd_data13.lcd_data13 */
			0xd8 (PULL_DISABLE | MUX_MODE7)		/* lcd_data14.lcd_data14 */
			0xdc (PULL_DISABLE | MUX_MODE7)		/* lcd_data15.lcd_data15 */
			0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
			0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_hsync.lcd_hsync */
			0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_pclk.lcd_pclk */
			0xec (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_ac_bias_en.lcd_ac_bias_en */
		>;
	};

#if 0
	user_leds_s0: user_leds_s0 {
                pinctrl-single,pins = <
                        0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad4.gpio1_4 */
			0x138 (PIN_INPUT_PULLUP | MUX_MODE7)
                >;
        };

	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
			0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
		>;
	};
#endif
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;

	status = "okay";
};

#if 0
&uart1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&uart1_pins_default>;
	pinctrl-1 = <&uart1_pins_sleep>;

	status = "okay";
};
#endif

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;

	status = "okay";
	clock-frequency = <400000>;

	tps: tps@2d {
		reg = <0x2d>;
	};
	
	gxlx680: gxlx680@40{
		compatible = "gslx680";
		reg = <0x40>;
	};

	ch7033: ch7033@76 {
		compatible = "chrontel,ch7033";
		reg = <0x76>;
		status = "okay";
	};
};

&usb {
	status = "okay";
};

&usb_ctrl_mod {
	status = "okay";
};

&usb0_phy {
	status = "okay";
};

&usb1_phy {
	status = "okay";
};

&usb0 {
	status = "okay";
	dr_mode = "host";
};

&usb1 {
	status = "okay";
	dr_mode = "host";
};

&cppi41dma  {
	status = "okay";
};
/*
&i2c1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c1_pins_default>;
	pinctrl-1 = <&i2c1_pins_sleep>;

	status = "okay";
	clock-frequency = <100000>;

};
*/
&lcdc {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&lcd_pins_default>;
	pinctrl-1 = <&lcd_pins_sleep>;
};

&elm {
	status = "okay";
};

/*
&epwmss2 {
	status = "okay";

	ecap2: ecap@48304100 {
		status = "okay";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&ecap2_pins_default>;
		pinctrl-1 = <&ecap2_pins_sleep>;
	};
};
*/

#include "tps65910.dtsi"


&tps {
	vcc1-supply = <&vbat>;
	vcc2-supply = <&vbat>;
	vcc3-supply = <&vbat>;
	vcc4-supply = <&vbat>;
	vcc5-supply = <&vbat>;
	vcc6-supply = <&vbat>;
	vcc7-supply = <&vbat>;
	vccio-supply = <&vbat>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1378000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1150000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd3_reg: regulator@4 {
			regulator-always-on;
		};

		vdig1_reg: regulator@5 {
			regulator-always-on;
		};

		vdig2_reg: regulator@6 {
			regulator-always-on;
		};

		vpll_reg: regulator@7 {
			regulator-always-on;
		};

		vdac_reg: regulator@8 {
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			regulator-always-on;
		};

		vaux33_reg: regulator@11 {
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
};

/*
&davinci_mdio {
	pinctrl-names = "default", "sleep";
	compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";

	dp83867_0: ethernet-phy@0 {
	reg = <0>;
	ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
	ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
	ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	ti,min-output-impedance;
	ti,dp83867-rxctrl-strap-quirk;
	};
};
*/

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <0>;
	phy-mode = "rgmii-txid";
};

/*
&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "rgmii-txid";
};
*/

&tscadc {
	status = "okay";
	tsc {
		ti,wires = <4>;
		ti,x-plate-resistance = <200>;
		ti,coordinate-readouts = <5>;
		ti,wire-config = <0x00 0x11 0x22 0x33>;
	};
	adc {
		ti,adc-channels = <4>;
	};

};

&mmc1 {
	status = "okay";
	vmmc-supply = <&vmmc_reg>;
	bus-width = <4>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_sleep>;
	cd-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
};

/*
&mmc2 {
        status = "okay";
        vmmc-supply = <&vmmc_reg>;
        bus-width = <8>;
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&mmc2_pins_default>;
        pinctrl-1 = <&mmc2_pins_sleep>;
        ti,non-removable;
};
*/

&sham {
	status = "okay";
};

&aes {
	status = "okay";
};

#if 0
&dcan1 {
	status = "disabled";	/* Enable only if Profile 1 is selected */
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_pins_default>;
};
#endif

&rtc {
	system-power-controller;
};

&sgx {
	status = "okay";
};

defconfig files:

am335x_b4_deconfig.txt

0 Schuyler Patton over 7 years ago in reply to Shiami

TI__Mastermind 40570 points

Hi,

Even though you have built in PHY support into the kernel is still reporting driver unknown. This is despite the fact the mdio driver is detecting a phy at the expected address in the dts file.

Could you please post the results of ethtool eth0? and ethtool -S eth0? I want to see if there is a link detected.

Regards,
Schuyler

0 Shiami over 7 years ago in reply to Schuyler Patton

Prodigy 70 points

Hi,

Thanks your help.

Using ethtool command "ethtool eth0", get the result "Link detected: no" which means mdio cannot recognize phy device?

The function "davinci_mdio_reset" of davinci_mdio.c in the kernel , always got wrong phy_mask, how regs get alive phy?

/* get phy mask from the alive register */
phy_mask = __raw_readl(&data->regs->alive);
if (phy_mask) {
	/* restrict mdio bus to live phys only */
	dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
	phy_mask = ~phy_mask;
} else {
	/* desperately scan all phys */
	dev_warn(data->dev, "no live phy, scanning all\n");
	phy_mask = 0;
}
data->bus->phy_mask = phy_mask;

ethtool eth0

Settings for eth0:

Supported ports: [ TP AUI BNC MII FIBRE ]

Supported link modes: 10baseT/Half

100baseT/Full

Supported pause frame use: No

Supports auto-negotiation: No

Advertised link modes: 10baseT/Half

100baseT/Full

Advertised pause frame use: No

Advertised auto-negotiation: No

Link partner advertised link modes: 10baseT/Full

100baseT/Full

Link partner advertised pause frame use: Transmit-only

Link partner advertised auto-negotiation: Yes

Speed: 100Mb/s

Duplex: Full

Port: MII

PHYAD: 0

Transceiver: external

Auto-negotiation: on

Supports Wake-on: d

Wake-on: d

Current message level: 0x00000000 (0)

Link detected: no

ethtool -S eth0
NIC statistics:
Good Rx Frames: 0
Broadcast Rx Frames: 0
Multicast Rx Frames: 0
Pause Rx Frames: 0
Rx CRC Errors: 0
Rx Align/Code Errors: 0
Oversize Rx Frames: 0
Rx Jabbers: 0
Undersize (Short) Rx Frames: 0
Rx Fragments: 0
Rx Octets: 0
Good Tx Frames: 0
Broadcast Tx Frames: 0
Multicast Tx Frames: 0
Pause Tx Frames: 0
Deferred Tx Frames: 0
Collisions: 0
Single Collision Tx Frames: 0
Multiple Collision Tx Frames: 0
Excessive Collisions: 0
Late Collisions: 0
Tx Underrun: 0
Carrier Sense Errors: 0
Tx Octets: 0
Rx + Tx 64 Octet Frames: 0
Rx + Tx 65-127 Octet Frames: 0
Rx + Tx 128-255 Octet Frames: 0
Rx + Tx 256-511 Octet Frames: 0
Rx + Tx 512-1023 Octet Frames: 0
Rx + Tx 1024-Up Octet Frames: 0
Net Octets: 0
Rx Start of Frame Overruns: 0
Rx Middle of Frame Overruns: 0
Rx DMA Overruns: 0
Rx DMA chan: head_enqueue: 1
Rx DMA chan: tail_enqueue: 63
Rx DMA chan: pad_enqueue: 0
Rx DMA chan: misqueued: 0
Rx DMA chan: desc_alloc_fail: 0
Rx DMA chan: pad_alloc_fail: 0
Rx DMA chan: runt_receive_buf: 0
Rx DMA chan: runt_transmit_buf: 0
Rx DMA chan: empty_dequeue: 0
Rx DMA chan: busy_dequeue: 0
Rx DMA chan: good_dequeue: 0
Rx DMA chan: requeue: 0
Rx DMA chan: teardown_dequeue: 0
Tx DMA chan: head_enqueue: 0
Tx DMA chan: tail_enqueue: 0
Tx DMA chan: pad_enqueue: 0
Tx DMA chan: misqueued: 0
Tx DMA chan: desc_alloc_fail: 0
Tx DMA chan: pad_alloc_fail: 0
Tx DMA chan: runt_receive_buf: 0
Tx DMA chan: runt_transmit_buf: 0
Tx DMA chan: empty_dequeue: 0
Tx DMA chan: busy_dequeue: 0
Tx DMA chan: good_dequeue: 0
Tx DMA chan: requeue: 0
Tx DMA chan: teardown_dequeue: 0

0 Shiami over 7 years ago in reply to Schuyler Patton

Prodigy 70 points

Hi,

Thanks your help.

Using ethtool command "ethtool eth0", get the result "Link detected: no" which means mdio cannot recognize phy device?

The function "davinci_mdio_reset" of davinci_mdio.c in the kernel , always got wrong phy_mask, how regs get alive phy?

ethtool eth0

Settings for eth0:

Supported ports: [ TP AUI BNC MII FIBRE ]

Supported link modes: 10baseT/Half

100baseT/Full

Supported pause frame use: No

Supports auto-negotiation: No

Advertised link modes: 10baseT/Half

100baseT/Full

Advertised pause frame use: No

Advertised auto-negotiation: No

Link partner advertised link modes: 10baseT/Full

100baseT/Full

Link partner advertised pause frame use: Transmit-only

Link partner advertised auto-negotiation: Yes

Speed: 100Mb/s

Duplex: Full

Port: MII

PHYAD: 0

Transceiver: external

Auto-negotiation: on

Supports Wake-on: d

Wake-on: d

Current message level: 0x00000000 (0)

Link detected: no

ethtool -S eth0
NIC statistics:
Good Rx Frames: 0
Broadcast Rx Frames: 0
Multicast Rx Frames: 0
Pause Rx Frames: 0
Rx CRC Errors: 0
Rx Align/Code Errors: 0
Oversize Rx Frames: 0
Rx Jabbers: 0
Undersize (Short) Rx Frames: 0
Rx Fragments: 0
Rx Octets: 0
Good Tx Frames: 0
Broadcast Tx Frames: 0
Multicast Tx Frames: 0
Pause Tx Frames: 0
Deferred Tx Frames: 0
Collisions: 0
Single Collision Tx Frames: 0
Multiple Collision Tx Frames: 0
Excessive Collisions: 0
Late Collisions: 0
Tx Underrun: 0
Carrier Sense Errors: 0
Tx Octets: 0
Rx + Tx 64 Octet Frames: 0
Rx + Tx 65-127 Octet Frames: 0
Rx + Tx 128-255 Octet Frames: 0
Rx + Tx 256-511 Octet Frames: 0
Rx + Tx 512-1023 Octet Frames: 0
Rx + Tx 1024-Up Octet Frames: 0
Net Octets: 0
Rx Start of Frame Overruns: 0
Rx Middle of Frame Overruns: 0
Rx DMA Overruns: 0
Rx DMA chan: head_enqueue: 1
Rx DMA chan: tail_enqueue: 63
Rx DMA chan: pad_enqueue: 0
Rx DMA chan: misqueued: 0
Rx DMA chan: desc_alloc_fail: 0
Rx DMA chan: pad_alloc_fail: 0
Rx DMA chan: runt_receive_buf: 0
Rx DMA chan: runt_transmit_buf: 0
Rx DMA chan: empty_dequeue: 0
Rx DMA chan: busy_dequeue: 0
Rx DMA chan: good_dequeue: 0
Rx DMA chan: requeue: 0
Rx DMA chan: teardown_dequeue: 0
Tx DMA chan: head_enqueue: 0
Tx DMA chan: tail_enqueue: 0
Tx DMA chan: pad_enqueue: 0
Tx DMA chan: misqueued: 0
Tx DMA chan: desc_alloc_fail: 0
Tx DMA chan: pad_alloc_fail: 0
Tx DMA chan: runt_receive_buf: 0
Tx DMA chan: runt_transmit_buf: 0
Tx DMA chan: empty_dequeue: 0
Tx DMA chan: busy_dequeue: 0
Tx DMA chan: good_dequeue: 0
Tx DMA chan: requeue: 0
Tx DMA chan: teardown_dequeue: 0

0 Schuyler Patton over 7 years ago in reply to Shiami

TI__Mastermind 40570 points

Hi,

Per your question that is correct, a link has to be detected. Based on the log capture above which is showing the PHY is not recognized and no link detected I would recommend looking at the PHY functionality. Some things to check is if the PHY is getting a good reset, the PHY strapping is correct, if the link partner is seeing a link detected. You may need to submit a post to the Ethernet forums that support the PHY you have chosen for additional information.

Regards,
Schuyler

Processors

Processors forum

Linux/AM3358: DP83867 PHY issue