RTOS/AM5728: PCIe ECRC test

Sangwook Han

Part Number: AM5728

Tool/software: TI-RTOS

Hi there,

Using AM5728/C66x/TI-RTOS, the AM5728 communicates with a FPGA by PCIe and It works well. However, I test ECRC test function but It doesn't work.

(AM5728 supposed to send a corrupted TX TLP, FPGA couldn't checked it).

To corrupt a PCIe TX TLP, I used PCIECTRL_TI_CONF_DIAG_CTRL register.

My questions are:

1. ECRC is always enabled?

2. My test code is shown below. Is this code send a corrupted TX TLP?

...
while(1)
	{
	    Task_sleep(1000);
	    irqRaised1 = 0;
	    retVal = pcieRcSendECRC(handle);
	    drvInst->shadowRegs->ESR = 1UL << 1;    //send PCIe TX TLP by DMA
	    while (!irqRaised1);
	}
...
}

pcieRet_e pcieRcSendECRC (Pcie_Handle handle)
{
  pcieRegisters_t             regs;
  pcieTiConfDiagCtrlReg_t   eCRCAssert;
  pcieRet_e                   retVal;

  PCIE_logPrintf ("RC sending ECRC to EP\n");

  /* Now send ECRC error TLP */
  memset (&regs, 0, sizeof(regs));
  memset (&eCRCAssert, 0, sizeof(eCRCAssert));

  /* Read the current value */
  regs.tiConfDiagCtrl = &eCRCAssert;
  retVal = Pcie_readRegs (handle, pcie_LOCATION_LOCAL, &regs);
  if (retVal != pcie_RET_OK){
      PCIE_logPrintf("Can't read ECRC control regs in ticonf\n");
      return pcie_RET_UNSUPPORTED;
  }

  if (eCRCAssert.invEcrc){
      PCIE_logPrintf("ECRC control already asserted\n");
  }
  else{
      /* Send it */
      eCRCAssert.invEcrc = 1U;
      retVal = Pcie_writeRegs (handle, pcie_LOCATION_LOCAL, &regs);
      if (retVal != pcie_RET_OK){
          PCIE_logPrintf("Can't write Ecrc control regs in ticonf\n");
          return pcie_RET_UNSUPPORTED;
      }
      else{
          PCIE_logPrintf("ECRC asserted\n");
      }
  }
  return pcie_RET_OK;
}

Thank you in advance

Sangwook Han

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

The RTOS team have been notified. They will respond here.

0 lding over 7 years ago in reply to Biser Gatchev-XID

TI__Guru* 95265 points

Hi,

I don't have test code for ECRC test. I need check internally and give back to you.

Regards, Eric

0 lding over 7 years ago in reply to lding

TI__Guru* 95265 points

Hi,

The ECRC is hardware feature. The AM57x is capable of generating and checking ECRC but I knew some FPGA doesn't support ECRC. From our PCIE driver code, we have ECRC enabling in "1118h PCIE_ACCR PCI Express Advanced Capabilities and Control Register" for Keystone PCIE, but not AM57x.

Do you have any tool like scope to make sure the PCIE TLP packet has ECRC bytes to check if AM57x ECRC generation is enabled?

Regards, Eric

0 Sangwook Han over 7 years ago in reply to lding

Prodigy 60 points

Thank you for reply Eric

Unfortunately, I don't have a such tool which scopes a PCIe packet. Therefore, I had to scope a received packet on RX side.

Xilinx Artix-7 is also capable of generating and checking ECRC. For example, if the FPGA received a corrupted TLP, it generated a error flag(rx_ecrc_err).

I ran above test code on AM5728 (C66x), then waited for an error flag on FPGA. However, I couldn't see in.

0 lding over 7 years ago in reply to Sangwook Han

TI__Guru* 95265 points

Hi,

Thanks! I think the first thing to find is on AM57x side, if ECRC generation is enabled or not. There is a set of registers called PCI Express Extended Capabilities Registers. Among them, offset 0x18 is PCIE_ACCR. This register has control ECRC generation.

However, in our PCIE driver, I didn't find those set of registers, neither in the AM57x TRM.

From PCIE Specification,
Extended Capabilities in device configuration space always begin at offset 100h with a PCI
Express Enhanced Capability Header (Section 5.9.3). Absence of any Extended Capabilities
is required to be indicated by an Enhanced Capability Header with a Capability ID of FFFFh
and a Next Capability Offset of 0h.

So I looked at 0x5100_1100 for a running PCIE system. This register value is a valid value 0x00020001. So the offset 0x18 is valid, the value is 0x0000_00a0, by decoding with PCIE Spec, this is:

5 ECRC Generation Capable – This bit indicates that
the device is capable of generating ECRC (see
Section 2.10).
RO
6 ECRC Generation Enable – This bit when set
enables ECRC generation (see Section 2.10).
RWS

7 ECRC Check Capable – This bit indicates that the
device is capable of checking ECRC (see
Section 2.10).
RO
8 ECRC Check Enable – This bit when set enables
ECRC checking (see Section 2.10).
Default value of this field is 0.
RWS

So, it looks that we are capable of generating ECRC and checking ECRC, but not enabled. You may try to set this register bit 8 and bit 6, *(unsigned int*) 0x5100_1118 = 0x1E0 (if you use PCIE SS1); then see the FPGA side can detect any ECRC error TLP.

Regards, Eric

0 Sangwook Han over 7 years ago in reply to lding

Prodigy 60 points

Thank you! Eric

I tried what you told, but It still didn't work. I'm not sure which one isn't worked; AM5728 or FPGA.

So, I'll try the other way around. FPGA will generate a corrupted TLP. AM5728 may detect the corrupted TLP then generate a interrupt event according to TRM page 6244: 24.9.4.6.1.2 PCIe Error Interrupt Events

After test, I'll let you know the result

Regards, Sangwook Han

0 lding over 7 years ago in reply to Sangwook Han

TI__Guru* 95265 points

Any news?

Regards, Eric

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RTOS/AM5728: PCIe ECRC test