Other Parts Discussed in Thread: TAS5558,
Hello,
I am trying to minimize the latency through the TAS5548. I have identified a couple parameters that allow me to drop the latency; however, it appears that the only real way to make the system as fast a possible is to bypass the ASRC entirely. This raises a bunch of problems since the device is designed to run as a I2S slave and does not accept a master clock input. The logical solution there is to move to the TAS5558, which is inexplicably 2X the price.
Base latency at 48kHz input and default config ~2.65ms.
Modify Register C4 from 32 sample FIFO to 16 sample FIFO reduces the latency by 16 samples. And a 48k input has a latency of ~2ms or 96 samples.
Modifying Register C5 so that the ASRC sampling rate = 192kHz reduces the latency again, And a 48kHz input has a latency of ~1.729ms with a 16 sample FIFO.
Moving to a faster input sample rate move latency again, and with a 192kHz input, 192kHz ASRC, and 16 sample FIFO I can get 0.6458ms of latency.
Are there any other places I can shave out some processing time?
The only other option is to run the TAS with the ASRC bypassed, which allows for ~125us of latency, but causes significant issues for my system design. Namely that the TAS5548 cannot accept an MCLK input. I know that the TAS5558 can, but i do not have another $1.40 in my BOM.
Thank you,
Adam
